What you will learn

• Boolean algebra laws
• De Morgan theorems
• Duality
• Logic gates
• Universal gates
• Minterms and maxterms
• SOP and POS
• Karnaugh maps
• Don't care conditions
• Prime implicants
• Half adder
• Full adder
• Half subtractor
• Full subtractor
• Parallel binary adder subtractor
• Carry look-ahead adder
• BCD adder
• Multiplexers
• De-multiplexers
• Decoders
• Encoders
• Priority encoders
• Latches
• SR flip-flop
• D flip-flop
• JK flip-flop
• T flip-flop
• Clocked flip-flop
• Race around condition
• Master-slave flip-flop
• Flip-flop conversion
• Excitation tables
• Registers
• Shift registers
• Universal shift register
• Asynchronous counters
• Synchronous counters
• Ring counter
• Johnson counter
• Register transfer language
• Micro-operations
• Bus transfer
• Memory transfer
• Arithmetic logic shift unit
• Instruction codes
• Computer registers
• Instruction cycle
• General register organization
• Stack organization
• Reverse polish notation
• Instruction formats
• Addressing modes
• Peripheral devices
• Input-output interfaces
• Isolated and memory-mapped I/O
• Asynchronous data transfer
• Strobe control
• Handshaking
• Programmed I/O
• Interrupt-driven I/O
• Priority interrupt
• Daisy chaining
• Direct memory access
• Main memory
• SRAM
• DRAM
• ROM
• Auxiliary memory
• Magnetic disk
• Associative memory
• Cache memory
• Direct mapping
• Associative mapping
• Set-associative mapping
• Replacement algorithms
• Virtual memory
• Paging
• Segmentation
• TLB
• Page replacement

Course content (49 lessons)

1. About This Course — Computer Organization and Architecture — University Course This course covers Computer Organization and Architecture (COA) as taught in undergraduate BCA / MCA / BTech university…
2. Unit I Overview: Boolean Algebra, Logic Gates and Arithmetic Circuits — Unit I: Boolean Algebra, Logic Gates and Arithmetic Circuits Unit I is the digital foundation of every CPU, memory chip, and I/O controller. Mastering it unlocks understanding of…
3. Unit 1 — Number Systems, Complements and Binary Codes — Why Number Systems Come First Every circuit in this course moves bits . Before you can design an adder you must know what the bits mean , how negative numbers are stored, and how…
4. Unit 1 — Boolean Algebra: Basic Laws and Postulates — Boolean Algebra Boolean algebra is the algebra of two-valued variables (0 and 1) developed by George Boole and applied to switching circuits by Claude Shannon in 1938. Every…
5. Unit 1 — De Morgan's Theorems and Complementation — De Morgan's Theorems De Morgan's theorems are the two most-used identities in all of digital design — they are what let a designer build any circuit out of only NAND gates or only…
6. Unit 1 — Logic Gates: Symbols, Truth Tables and Universal Gates — Logic Gates A logic gate is the physical circuit that implements a Boolean operation. Gates are the atoms of every digital system in this course. 1. The Seven Gates — Complete…
7. Unit 1 — Canonical Forms: Minterms, Maxterms, SOP and POS — Standard Forms of a Boolean Function Every Boolean function can be written in exactly two canonical (standard) ways. Both are derived directly from the truth table with zero…
8. Unit 1 — Karnaugh Maps: SOP Simplification (2, 3 and 4 Variables) — The Karnaugh Map A K-map is a truth table redrawn as a grid whose cells are arranged in Gray-code order , so that physically adjacent cells differ in exactly one variable.…
9. Unit 1 — K-Map POS Simplification — Minimum POS from a K-Map The K-map procedure for Product of Sums is identical to SOP with three changes: Why the inversion? Grouping the 0s gives you the minimum SOP of F' .…
10. Unit 1 — Don't Care Conditions — Don't Care Conditions A don't care (written X or d or φ ) is an input combination for which the output value is irrelevant — either because that input can never occur, or because…
11. Unit 1 — Arithmetic Circuits: Half Adder and Full Adder — Adders An adder is the combinational circuit that performs binary addition. It is the first genuinely useful circuit you can design with the tools from the previous lessons, and…
12. Unit 1 — Half Subtractor and Full Subtractor — Subtractors A subtractor computes A − B in binary, producing a difference and a borrow . 1. Half Subtractor Subtracts two bits: A − B . Note that the order matters — subtraction…
13. Unit 1 — Parallel Binary Adder / Subtractor and Carry Look-Ahead — Parallel Binary Adder A parallel (ripple-carry) adder adds two n-bit numbers by cascading n full adders, with each stage's carry-out wired to the next stage's carry-in. Worked…
14. Unit II Overview: Combinational Circuits and Flip-Flops — Combinational vs Sequential Digital Circuits --- Combinational vs Sequential Comparison Feature Combinational Sequential --- --- --- Memory None Has flip-flops / latches Feedback…
15. Unit 2 — Combinational Circuits: Design Procedure — Combinational vs Sequential Circuits Unit II covers both families. Knowing the difference is the first question of almost every paper. Basis Combinational Sequential --- --- ---…
16. Unit 2 — Multiplexers (Data Selectors) — Multiplexer A multiplexer (MUX) selects one of 2^n input lines and routes it to a single output, under the control of n select lines. It is a digitally controlled rotary switch.…
17. Unit 2 — De-Multiplexers (Data Distributors) — De-Multiplexer A de-multiplexer (DEMUX) takes a single data input and routes it to one of 2^n output lines, chosen by n select lines. It is the exact inverse of a multiplexer. 1.…
18. Unit 2 — Decoders — Decoder A decoder converts an n-bit binary code into 2^n output lines, activating exactly one of them. It answers the question: "which one of the 2^n possibilities does this code…
19. Unit 2 — Encoders and Priority Encoders — Encoder An encoder performs the inverse of a decoder: given 2^n input lines of which exactly one is active, it outputs the n-bit binary code of that line. 1. Octal-to-Binary…
20. Unit 2 — Sequential Circuits and Latches — From Combinational to Sequential Add a feedback path to a combinational circuit and something new appears: the output now depends on its own previous value. The circuit remembers…
21. Unit 2 — SR and D Flip-Flops — Clocked Flip-Flops A flip-flop is an edge-triggered 1-bit memory element. Unlike a latch, it samples its inputs only at the instant of a clock transition, which makes large…
22. Unit 2 — JK and T Flip-Flops, and the Race Around Condition — JK Flip-Flop The JK flip-flop is the SR flip-flop with the forbidden state turned into a useful one: J = K = 1 makes the output toggle . Characteristic table CLK J K Q(n+1)…
23. Unit 2 — Master-Slave Flip-Flop and Clocked Operation — Master-Slave Flip-Flop A master-slave flip-flop cascades two level-triggered flip-flops driven by complementary clocks , so that at no instant is the whole device transparent from…
24. Unit 2 — Realisation of One Flip-Flop Using Another — Flip-Flop Conversion Any flip-flop can be converted into any other by adding a small combinational network in front of its inputs. This is a guaranteed exam question, and the…
25. Unit 2 — Applications of Flip-Flops: Latches, Registers and Shift Registers — Registers A register is a group of n flip-flops sharing a common clock, storing an n-bit word. It is the fundamental storage unit inside a CPU — Unit III is built entirely on…
26. Unit 2 — Counters: Asynchronous, Synchronous, Ring and Johnson — Counters A counter is a sequential circuit that steps through a fixed sequence of states on successive clock pulses. It is the second great application of flip-flops (after…
27. Unit III Overview: Data Transfer Operations and Computer Organization — Fetch-Decode-Execute Cycle --- RTL Notation Reference Symbol Meaning Example --- --- --- ← Transfer (assign) R1 ← R2 (copy R2 into R1) M[addr] Memory at address DR ← M[AR] (read…
28. Unit 3 — Register Transfer Language and Micro-operations — Register Transfer Language (RTL) RTL is a symbolic notation for describing what a digital system does in terms of registers and the operations performed on the data stored in them…
29. Unit 3 — Bus and Memory Transfer — The Interconnection Problem 1. Common Bus System A bus is a set of common lines, one per bit, through which binary information is transferred one word at a time between registers.…
30. Unit 3 — Arithmetic, Logic and Shift Micro-operations: The ALU — Building the Hardware for Micro-operations The previous lessons named the micro-operations. This lesson builds the circuits that perform them — culminating in a complete…
31. Unit 3 — Instruction Codes and Computer Registers — Instruction Codes An instruction code is a group of bits that instructs the computer to perform a specific operation. It is the interface between software and the micro-operations…
32. Unit 3 — The Instruction Cycle: Fetch, Decode, Execute — The Instruction Cycle The CPU repeats one loop forever. Every phase is a sequence of micro-operations timed by a sequence counter (SC) whose outputs are decoded into timing…
33. Unit 3 — General Register Organization — Why General Registers? The basic computer of the previous lessons has one accumulator. Every operation must pass through AC and therefore through memory, which is slow. General…
34. Unit 3 — Stack Organization — Stack A stack is a storage device that stores information such that the item stored last is the first retrieved — LIFO (Last In, First Out). 1. Register Stack A stack implemented…
35. Unit 3 — Instruction Formats: Three, Two, One and Zero Address — Instruction Format The instruction format defines how the bits of an instruction word are divided into fields. The number of address fields classifies the CPU organization. The…
36. Unit 3 — Addressing Modes — Addressing Modes An addressing mode specifies a rule for interpreting or modifying the address field of an instruction before the operand is actually referenced. Key term: the…
37. Unit IV Overview: I/O Organization and Memory Hierarchy — I/O and Memory Organization Overview --- Memory Hierarchy (8 Levels) Level Type Technology Speed Cost/bit Typical Capacity Volatile? --- --- --- --- --- --- --- 1 CPU Registers…
38. Unit 4 — Peripheral Devices — Peripheral Devices Peripherals are the electromechanical and electromagnetic devices connected to a computer that provide input, output or auxiliary storage. They are outside the…
39. Unit 4 — Input-Output Interfaces — The I/O Interface Unit An I/O interface provides a method for transferring information between internal storage (CPU and memory) and external I/O devices. It resolves the speed,…
40. Unit 4 — Asynchronous Data Transfer — Synchronous vs Asynchronous Transfer 1. Strobe Control A single control line called a strobe announces the time at which data is valid. Source-initiated strobe…
41. Unit 4 — Modes of Transfer: Programmed I/O, Interrupt-Driven I/O and DMA — Three Modes of Transfer Data between memory and an I/O device can be transferred in three ways, differing in who supervises the transfer and what the CPU does meanwhile . 1.…
42. Unit 4 — Priority Interrupt Systems — The Priority Problem A priority interrupt system establishes a priority order among devices so that when several interrupt simultaneously, the one with the highest priority is…
43. Unit 4 — Direct Memory Access (DMA) — Direct Memory Access DMA is a transfer technique in which a dedicated controller moves data directly between an I/O device and memory, without routing it through the CPU . 1. Bus…
44. Unit 4 — Memory Hierarchy and Main Memory — The Memory Hierarchy No single memory technology is simultaneously fast, large and cheap. The solution is a hierarchy : a small fast memory close to the CPU backed by…
45. Unit 4 — Auxiliary Memory — Auxiliary (Secondary) Memory Auxiliary memory is non-volatile storage that is not directly addressable by the CPU . Its contents must first be transferred into main memory…
46. Unit 4 — Associative Memory (Content Addressable Memory) — Associative Memory Associative memory (Content Addressable Memory, CAM) is a memory unit accessed by the content of the data rather than by its address. All words are searched in…
47. Unit 4 — Cache Memory and Mapping Techniques — Cache Memory Cache memory is a small, fast memory placed between the CPU and main memory that holds copies of the most frequently used data and instructions. It works because of…
48. Unit 4 — Virtual Memory — Virtual Memory Virtual memory is a technique that allows a program to be executed even when it is not entirely in main memory. It gives every process the illusion of a large,…
49. 📄 PYQ — End Term Dec 2025

About This Course

Computer Organization and Architecture — University Course

This course covers Computer Organization and Architecture (COA) as taught in undergraduate BCA / MCA / BTech university programmes. The subject is unusual because it starts at the level of a single logic gate and ends at the level of a complete working computer — every unit is a floor built on the one below it.

Architecture vs Organization — the distinction every paper asks

One-line answer: An Intel Core i3 and an i9 share the same architecture (both run the same programs) but have very different organizations (cache sizes, core counts, pipeline depth).

Syllabus at a Glance:

What you will learn:

• How to reduce any Boolean expression by algebra and by K-map, including the don't-care shortcuts that examiners love
• How to build adders, subtractors, multiplexers, decoders an

Continue reading: About This Course →

Frequently asked questions

Is the Computer Organization and Architecture course really free?

Yes. The entire Computer Organization and Architecture course on Siksha Sarovar is free to read with no account required. You can optionally sign in with Google to save your progress.

Do I get a certificate for Computer Organization and Architecture?

Yes — finish the lessons and pass the quiz to earn a free, verifiable certificate you can share on LinkedIn or with recruiters.

Can I run code while learning?

Yes. The built-in online compiler runs C, C++, Python, Java, PHP, JavaScript, C# and SQL directly in your browser — no installation needed.