Computer Organization and Architecture — Free Notes & Tutorial
Free Computer Organization and Architecture course on SikshaSarovar (Siksha Sarovar) — 17 structured lessons with notes, examples and a built-in online compiler. 100% free, no sign-up required.
This Computer Organization and Architecture course is part of Siksha Sarovar and is 100% free for students in India — no sign-up required to read. It contains 17 structured lessons with examples, and pairs with our free online compiler and AI tutor.
Course content (17 lessons)
- Course Introduction: Computer Organization and Architecture — What is Computer Organization and Architecture? Computer Architecture — the attributes visible to the programmer: instruction set, data types, addressing modes, I/O mechanisms. It…
- Unit I Overview: Boolean Algebra, Logic Gates and Arithmetic Circuits — Unit I: Boolean Algebra, Logic Gates and Arithmetic Circuits Unit I is the digital foundation of every CPU, memory chip, and I/O controller. Mastering it unlocks understanding of…
- Logic Gates and Boolean Simplification — Logic Gate Family --- Combined Truth Table (2-input gates) A B AND (A·B) OR (A+B) NAND (A·B)' NOR (A+B)' XOR (A⊕B) XNOR (A⊙B) --- --- --- --- --- --- --- --- 0 0 0 0 1 1 0 1 0 1 0…
- Karnaugh Maps (K-Maps): SOP, POS and Don't Care Conditions — K-Map Simplification Process --- K-Map Grid Layouts 2-Variable K-Map (4 cells): AB 0 1 --- --- --- 0 m₀ m₁ 1 m₂ m₃ 3-Variable K-Map (8 cells) — Gray Code column order…
- Arithmetic Circuits: Half Adder, Full Adder, Subtractors and Parallel Adder — Half Adder Circuit --- Half Adder Truth Table A B Sum (A⊕B) Carry (A·B) --- --- --- --- 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Expressions: Sum = A ⊕ B, Carry = A · B A Half Adder adds…
- Unit II Overview: Combinational Circuits and Flip-Flops — Combinational vs Sequential Digital Circuits --- Combinational vs Sequential Comparison Feature Combinational Sequential --- --- --- Memory None Has flip-flops / latches Feedback…
- Combinational Circuits: Multiplexers, Demultiplexers, Decoders and Encoders — 4:1 Multiplexer (MUX) --- 2:1 MUX Truth Table S Y (Output) --- --- 0 I₀ 1 I₁ Expression: Y = S'·I₀ + S·I₁ --- 4:1 MUX Truth Table S₁ S₀ Y (Output) --- --- --- 0 0 I₀ 0 1 I₁ 1 0 I₂…
- Flip-Flops: SR, D, JK, T — Truth Tables, State Diagrams and Conversions — JK Flip-Flop State Diagram --- SR Flip-Flop Truth Table S R Q(t+1) Notes --- --- --- --- 0 0 Q(t) No change (memory) 0 1 0 Reset 1 0 1 Set 1 1 X Invalid/Forbidden — both outputs…
- Registers, Counters, Latches and The Master-Slave Flip-Flop — 4-Bit Serial-In Serial-Out (SISO) Shift Register --- SR Latch (NAND-Based) S (active-low) R (active-low) Q Q' --- --- --- --- 0 1 1 0 (Set) 1 0 0 1 (Reset) 1 1 Q Q' (Hold) 0 0 1 1…
- Unit III Overview: Data Transfer Operations and Computer Organization — Fetch-Decode-Execute Cycle --- RTL Notation Reference Symbol Meaning Example --- --- --- ← Transfer (assign) R1 ← R2 (copy R2 into R1) M[addr] Memory at address DR ← M[AR] (read…
- Register Transfer Language, Bus Structure and Memory Transfer — Single Bus Structure A single-bus architecture: only one transfer can occur per clock cycle. 3-state buffers (tri-state) allow multiple registers to share the bus — only one…
- Instruction Codes, Computer Registers and The Instruction Cycle — Instruction Cycle Flowchart --- Instruction Code Structure An instruction word consists of: - Opcode (Operation Code): specifies the operation (ADD, LOAD, JUMP, etc.) -…
- Stack Organization, Instruction Formats and All Addressing Modes — Addressing Mode Types --- Stack Organization A stack is a LIFO (Last-In, First-Out) data structure managed by the Stack Pointer (SP) . PUSH operation (SP grows toward high…
- Unit IV Overview: I/O Organization and Memory Hierarchy — I/O and Memory Organization Overview --- Memory Hierarchy (8 Levels) Level Type Technology Speed Cost/bit Typical Capacity Volatile? --- --- --- --- --- --- --- 1 CPU Registers…
- I/O Interfaces, Peripheral Devices and Asynchronous Data Transfer — Asynchronous Handshaking Protocol --- Peripheral Devices Reference Device Type Interface Typical Data Rate Notes --- --- --- --- --- Keyboard Input USB / PS/2 10 KB/s Human-speed,…
- Priority Interrupt Systems and DMA — Detailed Operation — Interrupt Handling Sequence --- Interrupt Types Category Type Definition Examples Maskable? --- --- --- --- --- Source Hardware interrupt Generated by hardware device Keyboard,…
- Memory Organization: Cache, Virtual, Associative and Auxiliary Memory — Memory Hierarchy Pyramid --- SRAM vs DRAM Comparison Feature SRAM DRAM --- --- --- Technology Bistable flip-flop (6 transistors per cell) Capacitor + transistor (1 transistor per…
Course Introduction: Computer Organization and Architecture
What is Computer Organization and Architecture?
Computer Architecture — the attributes visible to the programmer: instruction set, data types, addressing modes, I/O mechanisms. It answers what the computer does.
Computer Organization — the operational units and their interconnections: control signals, ALU design, memory interfaces. It answers how the computer does it.
Analogy: Architecture = car design specs (engine size, horsepower). Organization = actual engine parts (pistons, crankshaft, cooling) that implement those specs.
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Number Systems
| System | Base | Digits | Example: 42₁₀ | Conversion |
|---|---|---|---|---|
| Binary | 2 | 0, 1 | 101010₂ | Divide by 2; collect remainders LSB-first |
| Octal | 8 | 0–7 | 52₈ | Divide by 8; or group binary by 3 |
| Decimal | 10 | 0–9 | 42₁₀ | Native |
| Hexadecimal | 16 | 0–9, A–F | 2A₁₆ | Divide by 16; A=10…F=15 |
Verify: 101010₂=32+8+2=42 ✓ 52₈=5×8+2=42 ✓ 2A₁₆=2×16+10=42 ✓
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Course Roadmap
| Unit | Topics | Lessons | Hours |
|---|---|---|---|
| Unit I | Boolean Algebra, Logic Gates, K-Maps, Arithmetic Circuits | 3–5 | 12 |
| Unit II | Combinational Circuits, Flip-Flops, Registers, Counters | 6–9 | 12 |
| Unit III | RTL, Data Transfer, Instruction Cycles, Addressing Modes | 10–13 | 12 |
| Unit IV | I/O Organization, Interrupts, DMA, Memory Hierarchy | 14–17 | 12 |
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Von Neumann vs Harvard Architecture
| Feature | Von Neumann | Harvard |
|---|---|---|
| Memory | Unified — instructions and data share one memory | Separate memories for instructions and data |
| Bus | Single shared bus | Separate instruction and data buses |
| Bottleneck | Yes — instruction/data compete for bus | No — parallel access |
| Speed | Slower | Faster |
| Cost | Lower | Higher |
| Use Cases | Desktop PCs, laptops, servers | DSPs, microcontrollers; modern CPUs use split L1 cache |
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Key CPU Components Glossary
| Component | Full Form | Size | Function |
|---|---|---|---|
| ALU | Arithmetic Logic Unit | 8–64 bit | Arithmetic and logical operations |
| CU | Control Unit | — | Decodes instructions; generates control signals |
| PC | Program Counter | 16–64 bit | Address of the NEXT instruction to fetch |
| IR | Instruction Register | 16–64 bit | Holds CURRENT instruction being decoded |
| MAR | Memory Address Register | 16–64 bit | Address for pending memory read/write |
| MDR | Memory Data Register | 8–64 bit | Data being transferred to/from memory |
| ACC | Accumulator | 8–64 bit | Stores intermediate ALU results |
| Clock | System Clock | — | Synchronizes all oper
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Frequently asked questions
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Do I get a certificate for Computer Organization and Architecture?
Yes — finish the lessons and pass the quiz to earn a free, verifiable certificate you can share on LinkedIn or with recruiters.
Can I run code while learning?
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