The I/O Interface Unit

An I/O interface provides a method for transferring information between internal storage (CPU and memory) and external I/O devices. It resolves the speed, format, signal-level and protocol mismatches identified in the previous lesson.

1. Structure of an Interface Unit

   Every interface contains at least four registers:

   1. DATA REGISTER (buffer)  : holds the byte/word being transferred
   2. STATUS REGISTER         : flags — ready, busy, error, done
   3. CONTROL REGISTER        : commands from the CPU — start, stop, mode
   4. ADDRESS DECODER / CS    : recognises the addresses assigned to
                                this interface

   Plus:
      - Bus buffers (tri-state) so the interface can share the data bus
      - Timing and control logic
      - Device-specific circuitry (serialiser, level shifter, DAC/ADC...)

2. I/O Bus and Interface Modules

   The I/O bus carries three groups of lines:

      DATA lines     : the actual information
      ADDRESS lines  : which device / which register inside it
      CONTROL lines  : what to do (read, write, status, control)

   Typical control codes placed on the control lines:

      Control command : activate the device (e.g. start the motor,
                        rewind the tape). Does not transfer data.
      Status command  : test various status conditions in the interface.
      Data output     : the interface accepts a data item from the bus.
      Data input      : the interface places a data item on the bus.

3. Isolated I/O vs Memory-Mapped I/O

This comparison is a guaranteed exam question.

   Example — read a status byte from a device at port 0x40:

   Isolated I/O (8085):        IN 40H            ; AC <- port 40
   Memory-mapped (ARM):        LDR R1, [R0]      ; R0 = 0xE0000040

4. Example: The Intel 8255 Programmable Peripheral Interface

   A general-purpose interface chip with 24 I/O lines:

      Port A : 8 lines
      Port B : 8 lines
      Port C : 8 lines (can be split into two 4-bit halves)
      Control register : programs the direction and mode of each port

   Address decoding uses two lines A1 A0:
      00 -> Port A       10 -> Port C
      01 -> Port B       11 -> Control register

   The CPU writes a CONTROL WORD to the control register to configure
   each port as input or output — this is what "programmable" means.

   Bidirectional data transfer with the 8255:

      CPU -> Control register : set Port A = output, Port B = input
      CPU -> Port A           : data appears on the 8 output pins
      CPU <- Port B           : data on the 8 input pins is read

5. Serial Communication Interface — the UART

   UART = Universal Asynchronous Receiver Transmitter

   Transmit side: a PISO shift register converts a parallel byte
                  into a serial bit stream (Unit II!)
   Receive side : a SIPO shift register converts the serial stream
                  back into a parallel byte

   Also handles: start/stop bit framing, parity generation and checking,
                 baud rate generation, error flags.

6. Serial vs Parallel Transmission

   Why serial won: at gigahertz rates, the arrival times of parallel bits
   on different wires (CLOCK SKEW) diverge more than one bit period.
   A single serial lane with an embedded clock avoids this entirely.

7. Complete I/O Command Types

Summary

   Interface unit = data register + status register + control register
                    + address decoder + bus buffers

   Isolated I/O   : separate address space, IN/OUT instructions
   Memory-mapped  : shared address space, ordinary instructions

   The interface resolves the CPU-peripheral mismatch, but does NOT
   solve the SYNCHRONISATION problem: how does the CPU know the device
   is ready? That is the subject of the next lesson.