Logic Gates
A logic gate is the physical circuit that implements a Boolean operation. Gates are the atoms of every digital system in this course.
1. The Seven Gates — Complete Reference
| Gate | Expression | Symbol shape | 00 | 01 | 10 | 11 | Remember it as |
|---|---|---|---|---|---|---|---|
| AND | Y = A·B | D-shape | 0 | 0 | 0 | 1 | "all inputs 1" |
| OR | Y = A+B | curved shield | 0 | 1 | 1 | 1 | "any input 1" |
| NOT | Y = A' | triangle + bubble | 1 | – | 0 | – | inverter |
| NAND | Y = (A·B)' | AND + bubble | 1 | 1 | 1 | 0 | "not all 1" |
| NOR | Y = (A+B)' | OR + bubble | 1 | 0 | 0 | 0 | "none is 1" |
| XOR | Y = A⊕B | OR + extra curve | 0 | 1 | 1 | 0 | "inputs differ" |
| XNOR | Y = (A⊕B)' | XOR + bubble | 1 | 0 | 0 | 1 | "inputs are equal" |
2. XOR and XNOR — the two that appear in every adder
A XOR B = A'B + AB' (1 when inputs are DIFFERENT)
A XNOR B = A'B' + AB = (A XOR B)' (1 when inputs are SAME)Useful XOR properties (memorise these — they shorten many problems):
A ⊕ 0 = A A ⊕ 1 = A'
A ⊕ A = 0 A ⊕ A' = 1
A ⊕ B = B ⊕ A (commutative)
(A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) (associative)
If A ⊕ B = C then A ⊕ C = B and B ⊕ C = A (self-inverse)Multi-input XOR outputs 1 when the number of 1s is odd — this is exactly a parity generator.
3-input XOR: A⊕B⊕C
000 -> 0 001 -> 1 010 -> 1 011 -> 0
100 -> 1 101 -> 0 110 -> 0 111 -> 1 (odd number of 1s -> 1)3. Positive vs Negative Logic
| Convention | HIGH voltage means | LOW voltage means |
|---|---|---|
| Positive logic | logic 1 | logic 0 |
| Negative logic | logic 0 | logic 1 |
A gate that is an AND in positive logic behaves as an OR in negative logic. The physical circuit never changes — only our naming convention does. This is De Morgan expressed in hardware.
4. Universal Gates — NAND and NOR
A gate is universal if every Boolean function can be realised using only that gate. NAND and NOR are both universal.
All basic gates from NAND
NOT A = NAND(A, A) 1 gate
A AND B = NAND( NAND(A,B), NAND(A,B) ) 2 gates (NAND then invert)
A OR B = NAND( NAND(A,A), NAND(B,B) ) 3 gates (invert inputs, then NAND)
A NOR B = NOT( A OR B ) 4 gates
A XOR B = NAND( NAND(A, NAND(A,B)),
NAND(NAND(A,B), B) ) 4 gates
Count: NOT = 1, AND = 2, OR = 3, XOR = 4, NOR = 4 NAND gatesAll basic gates from NOR
NOT: 1 NOR gate OR: 2 NOR gates AND: 3 NOR gates
XNOR: 4 NOR gates NAND: 4 NOR gatesXOR built from 4 NAND gates
Let X = (AB)'
Then Y = (A.X)' = (A(AB)')'
Z = (X.B)' = ((AB)'B)'
F = (Y.Z)' = A ⊕ B
Verify with A=1, B=0:
X = (1.0)' = 1; Y = (1.1)' = 0; Z = (1.0)' = 1; F = (0.1)' = 1 ✓5. Gate Count Comparison
| Function | Using AND/OR/NOT | Using NAND only | Using NOR only |
|---|---|---|---|
| NOT | 1 | 1 | 1 |
| AND | 1 | 2 | 3 |
| OR | 1 | 3 | 2 |
| NAND | 2 | 1 | 4 |
| NOR | 2 | 4 | 1 |
| XOR | 5 (3 gates min) | 4 | 5 |
6. Real ICs (the 74-series you use in the lab)
| IC | Contents |
|---|---|
| 7400 | Quad 2-input NAND |
| 7402 | Quad 2-input NOR |
| 7404 | Hex inverter |
| 7408 | Quad 2-input AND |
| 7432 | Quad 2-input OR |
| 7486 | Quad 2-input XOR |
| 7483 | 4-bit binary full adder |
7. Gate Parameters You May Be Asked to Define
| Parameter | Meaning |
|---|---|
| Propagation delay | Time from an input change to the corresponding output change (t_pLH, t_pHL) |
| Fan-in | Number of inputs a gate can accept |
| Fan-out | Number of similar gate inputs one output can drive |
| Noise margin | Maximum noise voltage tolerated without a false logic change |
| Power dissipation | Power consumed by the gate, typically in mW |
| Figure of merit | Speed–power product = propagation delay × power dissipation (lower is better) |
8. Implementing an Expression Gate by Gate
F = A.B + C'.D
Level 1: inverter for C
Level 2: AND(A, B) and AND(C', D)
Level 3: OR of the two AND outputs
Gate count: 1 NOT + 2 AND + 1 OR = 4 gates, 3 levels
Propagation delay = 3 x t(pd)Any SOP expression is a two-level AND-OR circuit; any POS expression is a two-level OR-AND circuit. Getting to the minimum two-level form is the job of the next two lessons.