From Combinational to Sequential
Add a feedback path to a combinational circuit and something new appears: the output now depends on its own previous value. The circuit remembers.
| Latch | Flip-Flop | |
|---|---|---|
| Triggering | Level sensitive (transparent while enabled) | Edge sensitive (samples at the transition) |
| Clock | Enable / no clock | Clock required |
| Output during active period | Follows the input continuously | Changes only at the edge |
| Speed / area | Faster, smaller | Slower, larger |
| Design use | Asynchronous designs, temporary storage | Synchronous designs (almost all modern logic) |
1. SR Latch with NOR Gates
Two cross-coupled NOR gates:
Q = (R + Q')'
Q' = (S + Q )'
S = SET input, R = RESET input.| S | R | Q(next) | State name |
|---|---|---|---|
| 0 | 0 | Q (no change) | Hold — memory! |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ? | Invalid / forbidden |
Why S = R = 1 is forbidden (NOR version):
Both outputs are forced to 0, so Q = Q' = 0 — a contradiction.
Worse, when both inputs return to 0 simultaneously, the final state
depends on which gate is faster -> a RACE CONDITION with an
unpredictable result.2. SR Latch with NAND Gates (S'R' latch)
Two cross-coupled NAND gates, ACTIVE LOW inputs:
Q = (S' . Q')'
Q' = (R' . Q )'| S' | R' | Q(next) | State |
|---|---|---|---|
| 0 | 0 | ? | Invalid |
| 0 | 1 | 1 | Set |
| 1 | 0 | 0 | Reset |
| 1 | 1 | Q | Hold |
Note the inversion: for the NOR latch the forbidden combination is 11 and the hold combination is 00; for the NAND latch it is the opposite.
3. Gated (Clocked) SR Latch
Add an enable/clock so the latch only responds when permitted:
S(internal) = S . EN
R(internal) = R . EN
EN = 0 -> latch HOLDS regardless of S and R
EN = 1 -> latch behaves as an ordinary SR latch (transparent)4. D Latch — eliminating the forbidden state
Tie R = S' so the two inputs can never both be 1:
D latch: S = D, R = D'
EN = 1 -> Q follows D (TRANSPARENT)
EN = 0 -> Q holds the last D (LATCHED / OPAQUE)| EN | D | Q(next) |
|---|---|---|
| 0 | X | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The D latch is the standard 1-bit storage cell — this is what a static RAM bit and a register bit are built from.
5. Characteristic Table, Equation and Excitation Table
Three tables describe every storage element. Learn the difference — examiners test it.
| Table | Question it answers | Direction |
|---|---|---|
| Characteristic table | Given the inputs and present state, what is the next state? | inputs → next state |
| Characteristic equation | The same relationship as a Boolean formula | inputs → next state |
| Excitation table | Given the required state transition, what inputs are needed? | required transition → inputs |
SR latch
Characteristic equation: Q(next) = S + R'.Q with the constraint S.R = 0Excitation table (SR):
| Q → Q(next) | S | R |
|---|---|---|
| 0 → 0 | 0 | X |
| 0 → 1 | 1 | 0 |
| 1 → 0 | 0 | 1 |
| 1 → 1 | X | 0 |
D latch
Characteristic equation: Q(next) = DExcitation table (D): trivially, D = Q(next).
6. Timing Parameters
| Parameter | Meaning |
|---|---|
| Setup time (t_su) | Data must be stable before the active clock edge |
| Hold time (t_h) | Data must remain stable after the active clock edge |
| Propagation delay (t_pd) | Clock edge to valid output |
| Metastability | If setup/hold is violated, the output can hover between 0 and 1 for an unbounded time |
Maximum clock frequency of a synchronous circuit:
T(min) = t_pd(FF) + t_pd(combinational logic) + t_su
f(max) = 1 / T(min)
Example: t_pd(FF) = 2 ns, logic = 5 ns, t_su = 1 ns
T(min) = 8 ns -> f(max) = 125 MHz7. The Transparency Problem
While EN = 1, a level-sensitive latch is TRANSPARENT:
any change on D passes straight through to Q.
In a circuit where Q feeds back into the logic that computes D,
the new Q can race around the loop and change D again within the
SAME enable pulse -> multiple unwanted state changes.This is the root cause of the race around condition you will meet with the JK flip-flop, and the reason edge-triggered flip-flops exist. The next lessons build them.
Summary
| Element | Inputs | Forbidden state | Characteristic equation |
|---|---|---|---|
| SR latch (NOR) | S, R | S = R = 1 | Q(n) = S + R'Q |
| SR latch (NAND) | S', R' | S' = R' = 0 | same with active-low inputs |
| Gated SR latch | S, R, EN | S = R = 1 while EN = 1 | Q(n) = S·EN + (R·EN)'·Q |
| D latch | D, EN | none | Q(n) = D (while EN = 1) |