Half Adder Circuit

---

Half Adder Truth Table

Expressions: Sum = A ⊕ B, Carry = A · B

A Half Adder adds two single bits but cannot accept a carry-in. It needs two inputs (A, B) and produces two outputs (Sum, Carry).

---

Full Adder Truth Table

Expressions:

• Sum = A ⊕ B ⊕ Cᵢₙ
• Cₒᵤₜ = AB + BCᵢₙ + ACᵢₙ (carry generated if any two of A, B, Cᵢₙ are 1)

---

---

Ripple Carry Adder Trace: 0101 + 0011

Result: 0101 (5) + 0011 (3) = 1000 (8) ✓

In a Ripple Carry Adder, carry ripples from bit 0 to bit N sequentially. For n bits, worst-case delay = n × (Full Adder delay) → slow for large n.

---

Half Subtractor

Expressions: Diff = A ⊕ B, Borrow = A' · B

---

Full Subtractor

Expressions: Diff = A ⊕ B ⊕ Bᵢₙ, Bₒᵤₜ = A'B + A'Bᵢₙ + BBᵢₙ

---

2's Complement Subtraction

To compute A − B: add A + (2's complement of B) = A + B' + 1

Example: 0101 − 0011 = 0101 + (1101) = 10010 → drop carry → 0010 (= 2) ✓

---

Study Deep: Carry Look-Ahead Adder (CLA)

CLA computes all carry bits simultaneously using:

• Generate: Gᵢ = AᵢBᵢ (this stage always produces carry)
• Propagate: Pᵢ = Aᵢ ⊕ Bᵢ (this stage propagates incoming carry)
• Carry: Cᵢ₊₁ = Gᵢ + PᵢCᵢ

All Cᵢ are computed in parallel in just 2 gate delays. For 4-bit CLA: always 2 gate delays regardless of carry chain length.

---

Adder Comparison Table

📝 Exam Tips: - Half Adder = 2 inputs, 2 outputs (Sum, Carry). Full Adder = 3 inputs, 2 outputs - Full Adder can be built from 2 Half Adders + 1 OR gate - CLA reduces delay from O(n) to O(log n) at cost of more hardware - Subtraction using 2's complement: A − B = A + NOT(B) + 1