JK Flip-Flop State Diagram

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SR Flip-Flop Truth Table

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D Flip-Flop Truth Table

D flip-flop simply captures the D input on the clock edge. The invalid state of SR is eliminated by tying S=D and R=D'.

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JK Flip-Flop Truth Table

JK is the most versatile flip-flop — no invalid state, has toggle mode.

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T Flip-Flop Truth Table

T flip-flop: T=0 hold, T=1 toggle. Built from JK with J=K=T.

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SR Flip-Flop State Diagram

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Excitation Tables

Excitation tables show what inputs are needed to achieve a desired state transition (used in sequential circuit design).

SR Flip-Flop Excitation:

JK Flip-Flop Excitation:

D Flip-Flop Excitation: Q(t+1) = D → D = Q(t+1) always.

T Flip-Flop Excitation: T = Q(t) ⊕ Q(t+1).

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FF Conversion: JK to D Flip-Flop

To implement D flip-flop using JK flip-flop:

• When D=0: need Q(t+1)=0 → J=0, K=X → set J=D=0, K=D'=1
• When D=1: need Q(t+1)=1 → J=1, K=X → set J=D=1, K=D'=0

Result: J = D, K = D' (feed D to J and NOT D to K)

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Race-Around Condition and Master-Slave

In a level-triggered JK FF with J=K=1: during clock HIGH, output toggles multiple times (races around). This is the race-around condition.

Master-Slave solution: Two flip-flops in cascade. Master captures input when CLK=1. Slave updates output when CLK=0. Output changes only once per clock cycle, eliminating race-around.

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Comparison Table

📝 Exam Tips: - SR: S=R=1 is forbidden. JK: J=K=1 causes toggle (not forbidden) - D FF: Q(t+1) = D — simplest excitation - Edge-triggered FFs sample input only at clock edge, avoiding race-around - Master-slave JK eliminates race-around: master loads on CLK=1, slave fires on CLK=0