Clocked Flip-Flops

A flip-flop is an edge-triggered 1-bit memory element. Unlike a latch, it samples its inputs only at the instant of a clock transition, which makes large synchronous systems predictable.

   Triggering types:

   Positive (rising) edge   ->  clock symbol with a triangle at the C input
   Negative (falling) edge  ->  triangle + bubble
   Level (latch)            ->  no triangle

1. SR Flip-Flop

Symbol and inputs

   Inputs : S (set), R (reset), CLK
   Outputs: Q, Q'

Characteristic (truth) table

   Characteristic equation:   Q(n+1) = S + R'.Q(n)      with S.R = 0

K-map derivation of the characteristic equation

              S R
         00     01     11     10
       +------+------+------+------+
  Q=0  |  0   |  0   |  X   |  1   |
       +------+------+------+------+
  Q=1  |  1   |  0   |  X   |  1   |
       +------+------+------+------+

   Group m(S=1,R=0) both rows      ->  S.R'  ... enlarge with the X cells:
   Group S=1 column pair (SR=10,11) ->  S
   Group Q=1, R=0 (SR=00,10)        ->  Q.R'

   Q(n+1) = S + R'Q       ✓

Excitation table (used in counter design)

State diagram

Drawback: the SR = 11 combination is invalid, so a designer must guarantee it never occurs. The D and JK flip-flops both remove this burden.

2. D Flip-Flop (Data / Delay Flip-Flop)

The most-used flip-flop in the world. Every register, every pipeline stage, every FPGA cell is a D flip-flop.

   Built from an SR flip-flop:   S = D,  R = D'
   The invalid state becomes structurally impossible.

Characteristic table

   Characteristic equation:   Q(n+1) = D

   In words: "whatever D is at the clock edge becomes Q, and stays
   there for one full clock period."  Hence the name DELAY flip-flop.

Excitation table

(The simplest excitation table of all: D = Q(n+1).)

Timing waveform

   CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_
   D     __|‾‾‾‾‾‾|____|‾‾|____
   Q     ____|‾‾‾‾‾‾|____|‾‾|__

   Q changes ONLY on rising edges, and always lags D by up to one clock period.

3. Asynchronous Inputs — Preset and Clear

Real flip-flop ICs have two extra inputs that override the clock:

   PRESET (PR)  : forces Q = 1 immediately, regardless of CLK and D
   CLEAR  (CLR) : forces Q = 0 immediately, regardless of CLK and D

   Usually ACTIVE LOW (drawn with bubbles), and asserting both at once
   is forbidden for the same reason SR = 11 is.

Use: system reset. On power-up every flip-flop is in a random state; a global CLEAR pulse forces a known starting state.

4. Edge Detection — how edge triggering is actually built

   A short pulse is generated at the clock transition using the
   propagation delay of an inverter:

      CLK ----+----------------\
              |                 AND ---> narrow pulse at the RISING edge
              +--[3 inverters]--/  (delayed and inverted CLK)

   The AND output is 1 only for the few nanoseconds where CLK is already
   high but the delayed inverted copy has not yet fallen.

Modern flip-flops use a master-slave or true edge-triggered (6-gate) structure instead — covered two lessons ahead.

5. D Flip-Flop Applications

D flip-flop as a divide-by-2 counter

   Connect D = Q'

   Q(n+1) = D = Q(n)'      -> the output TOGGLES on every clock edge

   CLK:  1  2  3  4  5  6
   Q  :  1  0  1  0  1  0     ->  Q has HALF the clock frequency  ✓

6. Comparison

The next flip-flop, JK, keeps the two-input flexibility of SR and removes the invalid state — but introduces a new problem of its own.