Computer Organization and Architecture — University Course
This course covers Computer Organization and Architecture (COA) as taught in undergraduate BCA / MCA / BTech university programmes. The subject is unusual because it starts at the level of a single logic gate and ends at the level of a complete working computer — every unit is a floor built on the one below it.
Architecture vs Organization — the distinction every paper asks
| Basis | Computer Architecture | Computer Organization |
|---|---|---|
| Question answered | What does the machine do? | How does it do it? |
| Visible to | The programmer / compiler writer | The hardware designer |
| Deals with | Instruction set, data types, addressing modes, registers visible to software, I/O mechanisms | Control signals, ALU circuitry, memory interfaces, bus widths, timing |
| Changes | Rarely (breaks software compatibility) | Often (same architecture, new implementation) |
| Example | "x86-64 has a MUL instruction" | "This chip implements MUL with a Wallace-tree multiplier in 3 cycles" |
One-line answer: An Intel Core i3 and an i9 share the same architecture (both run the same programs) but have very different organizations (cache sizes, core counts, pipeline depth).
Syllabus at a Glance:
| Unit | Topics |
|---|---|
| Unit I | Boolean algebra — basic laws; logic gates; simplification of Boolean equations using K-maps (SOP and POS); don't care conditions. Arithmetic circuits — adder, subtractor, parallel binary adder/subtractor |
| Unit II | Combinational circuits — multiplexers, de-multiplexers, decoders, encoders. Flip-flops — S-R, D, J-K, T, clocked flip-flop, race around condition, master-slave flip-flop, realisation of one flip-flop using another, applications: latch, registers, counters |
| Unit III | Data transfer operations — register transfer, bus and memory transfer, registers and micro-operations. Basic computer organization and design — instruction codes, computer registers, instruction cycle, general register organization, stack organization, instruction formats, addressing modes |
| Unit IV | Input-output organization — peripheral devices, I/O interfaces, asynchronous data transfer, modes of transfer, priority interrupt, DMA. Memory organization — main memory, auxiliary memory, associative memory, cache memory, virtual memory |
What you will learn:
- How to reduce any Boolean expression by algebra and by K-map, including the don't-care shortcuts that examiners love
- How to build adders, subtractors, multiplexers, decoders and encoders gate by gate — and how a MUX can implement any function
- How every flip-flop works, why the JK flip-flop races, how master-slave fixes it, and how to convert any flip-flop into any other using excitation tables
- How registers, shift registers and counters are assembled from flip-flops
- Register Transfer Language — the notation used to describe what a CPU does in a single clock cycle
- The complete instruction cycle of a basic computer: fetch, decode, execute — with the exact micro-operations at each timing signal
- Every addressing mode, with a single worked numerical you can reuse in the exam
- How the CPU talks to the outside world: handshaking, interrupts, daisy-chain priority and DMA
- The complete memory hierarchy — cache mapping numericals, associative memory, and virtual memory address translation
How the units connect
Notation used throughout this course: the complement of A is written A' (spoken "A bar"). AND is written as A·B or simply AB, OR as A + B, XOR as A ⊕ B.
PYQ papers and unit-wise important questions are available at the end of the lesson list.