Siksha Sarovar

Siksha Sarovar (sikshasarovar.com) is a free educational web application that helps students in India learn programming and prepare for academic and competitive exams. The platform offers structured coding courses (C, C++, Python, Java, HTML, CSS, PHP, Power BI, AI, Machine Learning, Data Science), complete university curriculum notes for BCA/MCA students with previous year question papers, Class 10 and Class 12 CBSE/HBSE school notes, and dedicated preparation material for SSC, UPSC, Banking, Railway and other government exams. Browsing the site is completely free and requires no account. Users may optionally sign in with Google solely to save their learning progress, quiz scores and personal preferences across devices.

Privacy Policy | Terms of Service | Contact Siksha Sarovar | About Siksha Sarovar

v4.0.9 · PWA
Siksha Sarovar logo
Siksha Sarovar
Your Learning Universe

Siksha Sarovar is a free e-learning platform for coding courses, BCA university notes and competitive exam preparation. Optional Google sign-in saves your learning progress across devices.

Initializing knowledge base…
Compiling modules 0%

Course Introduction: Computer Organization and Architecture

Lesson 1 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

What is Computer Organization and Architecture?

Computer Architecture — the attributes visible to the programmer: instruction set, data types, addressing modes, I/O mechanisms. It answers what the computer does.

Computer Organization — the operational units and their interconnections: control signals, ALU design, memory interfaces. It answers how the computer does it.

Analogy: Architecture = car design specs (engine size, horsepower). Organization = actual engine parts (pistons, crankshaft, cooling) that implement those specs.

---

Number Systems

SystemBaseDigitsExample: 42₁₀Conversion
Binary20, 1101010₂Divide by 2; collect remainders LSB-first
Octal80–752₈Divide by 8; or group binary by 3
Decimal100–942₁₀Native
Hexadecimal160–9, A–F2A₁₆Divide by 16; A=10…F=15

Verify: 101010₂=32+8+2=42 ✓ 52₈=5×8+2=42 ✓ 2A₁₆=2×16+10=42 ✓

---

---

Course Roadmap

UnitTopicsLessonsHours
Unit IBoolean Algebra, Logic Gates, K-Maps, Arithmetic Circuits3–512
Unit IICombinational Circuits, Flip-Flops, Registers, Counters6–912
Unit IIIRTL, Data Transfer, Instruction Cycles, Addressing Modes10–1312
Unit IVI/O Organization, Interrupts, DMA, Memory Hierarchy14–1712

---

Von Neumann vs Harvard Architecture

FeatureVon NeumannHarvard
MemoryUnified — instructions and data share one memorySeparate memories for instructions and data
BusSingle shared busSeparate instruction and data buses
BottleneckYes — instruction/data compete for busNo — parallel access
SpeedSlowerFaster
CostLowerHigher
Use CasesDesktop PCs, laptops, serversDSPs, microcontrollers; modern CPUs use split L1 cache

---

Key CPU Components Glossary

ComponentFull FormSizeFunction
ALUArithmetic Logic Unit8–64 bitArithmetic and logical operations
CUControl UnitDecodes instructions; generates control signals
PCProgram Counter16–64 bitAddress of the NEXT instruction to fetch
IRInstruction Register16–64 bitHolds CURRENT instruction being decoded
MARMemory Address Register16–64 bitAddress for pending memory read/write
MDRMemory Data Register8–64 bitData being transferred to/from memory
ACCAccumulator8–64 bitStores intermediate ALU results
ClockSystem ClockSynchronizes all operations; measured in GHz

---

Study Deep: Why COA Matters for Software Engineers

  • Performance: Cache-friendly code, data alignment, loop unrolling — all require understanding the memory hierarchy
  • Debugging: Reading disassembly requires knowledge of instruction formats, registers, and addressing modes
  • Security: Spectre, Meltdown, buffer overflows, ROP attacks — all exploit architectural features
  • Embedded systems: Firmware directly manipulates memory-mapped hardware registers
  • Compilers: Instruction selection, register allocation, and pipeline scheduling all require deep ISA knowledge
📝 Exam Tip: Classic question — What is the Von Neumann bottleneck? The CPU processes data far faster than it can be fetched from memory; the shared bus limits throughput. Harvard architecture and cache memory address this.