Instruction Format

The instruction format defines how the bits of an instruction word are divided into fields.

   Typical fields:

   +--------+-----------+-----------+-----------+------+
   | Opcode | Operand 1 | Operand 2 | Operand 3 | Mode |
   +--------+-----------+-----------+-----------+------+

   1. OPERATION CODE  : specifies the operation
   2. ADDRESS FIELD(S): memory address or register number
   3. MODE FIELD      : how the address field is to be interpreted

The number of address fields classifies the CPU organization.

The Standard Comparison Problem

Evaluate X = (A + B) × (C + D) using each instruction format.

This single problem appears in almost every COA paper. Learn all five answers.

1. Three-Address Instructions

   ADD  R1, A, B      ; R1 <- M[A] + M[B]
   ADD  R2, C, D      ; R2 <- M[C] + M[D]
   MUL  X,  R1, R2    ; M[X] <- R1 * R2

   Instructions: 3        Memory references: 3 (fetch) + 4 (read) + 1 (write) = 8

2. Two-Address Instructions

   MOV  R1, A         ; R1 <- M[A]
   ADD  R1, B         ; R1 <- R1 + M[B]
   MOV  R2, C         ; R2 <- M[C]
   ADD  R2, D         ; R2 <- R2 + M[D]
   MUL  R1, R2        ; R1 <- R1 * R2
   MOV  X,  R1        ; M[X] <- R1

   Instructions: 6

The destination doubles as one of the sources — this is the format used by x86 and most CISC machines.

3. One-Address Instructions (accumulator machine)

   LOAD  A            ; AC <- M[A]
   ADD   B            ; AC <- AC + M[B]
   STORE T            ; M[T] <- AC        (T is a temporary location)
   LOAD  C            ; AC <- M[C]
   ADD   D            ; AC <- AC + M[D]
   MUL   T            ; AC <- AC * M[T]
   STORE X            ; M[X] <- AC

   Instructions: 7    (and one temporary memory location is needed)

4. Zero-Address Instructions (stack machine)

   PUSH  A            ; TOS <- A
   PUSH  B            ; TOS <- B
   ADD                ; TOS <- (A + B)
   PUSH  C            ; TOS <- C
   PUSH  D            ; TOS <- D
   ADD                ; TOS <- (C + D)
   MUL                ; TOS <- (A+B) * (C+D)
   POP   X            ; M[X] <- TOS

   Instructions: 8    (but ADD, MUL and the arithmetic ops carry NO address)

5. RISC / Load-Store Instructions

   LOAD  R1, A        ; R1 <- M[A]
   LOAD  R2, B        ; R2 <- M[B]
   LOAD  R3, C        ; R3 <- M[C]
   LOAD  R4, D        ; R4 <- M[D]
   ADD   R1, R1, R2   ; R1 <- R1 + R2
   ADD   R3, R3, R4   ; R3 <- R3 + R4
   MUL   R1, R1, R3   ; R1 <- R1 * R3
   STORE X,  R1       ; M[X] <- R1

   Instructions: 8
   Memory references: only in LOAD and STORE (5 total data accesses)

The RISC rule: only LOAD and STORE access memory; every arithmetic instruction works register-to-register. This makes every instruction the same length and makes pipelining straightforward.

Complete Comparison Table

Instruction Length Trade-offs

   Longer instructions:
      + More addresses, more opcodes, larger address range
      - More memory used, slower fetch, more bus traffic

   Shorter instructions:
      + Compact code, faster fetch
      - Fewer operations, restricted addressing

   FIXED length (RISC): easy to decode, easy to pipeline, wastes bits
   VARIABLE length (CISC): compact, but decoding is complex

Expanding Opcode Technique

When the opcode field must accommodate more instructions than its width allows, use an expanding (variable-length) opcode.

   16-bit instruction, three 4-bit register addresses:

   Format 1 (3 addresses): 4-bit opcode + 4 + 4 + 4
        opcodes 0000 to 1110  ->  15 three-address instructions
        opcode 1111 = ESCAPE

   Format 2 (2 addresses): 1111 + 4-bit opcode + 4 + 4
        opcodes 0000 to 1110  ->  14 two-address instructions
        1111 1111 = ESCAPE again

   Format 3 (1 address): 1111 1111 + 4-bit opcode + 4
        ->  15 one-address instructions

   Format 4 (0 addresses): 1111 1111 1111 + 4-bit opcode
        ->  16 zero-address instructions

   Total instructions: 15 + 14 + 15 + 16 = 60, all in 16-bit words.

Standard Numericals

   Q1: A computer has a 32-bit instruction word split into an opcode,
       a register field of 6 bits, and an address field. If there are
       120 instructions, how large is the address field?

       Opcode bits = ceil(log2 120) = 7
       Address field = 32 - 7 - 6 = 19 bits

   Q2: A machine has 16-bit instructions, 32 registers, and a
       two-address register-register format. How many opcodes are possible?

       Register fields = 2 x log2(32) = 2 x 5 = 10 bits
       Opcode bits = 16 - 10 = 6  ->  2^6 = 64 opcodes

   Q3: A processor has 64 KB of memory and 8-bit words. An instruction
       consists of an opcode and one memory address. If 100 instructions
       must be supported, what is the minimum instruction size?

       Address bits = log2(64K) = 16
       Opcode bits  = ceil(log2 100) = 7
       Minimum size = 23 bits -> rounded to 24 bits (3 bytes)

Summary

   Instruction = opcode + address field(s) + mode field
   3-address : shortest program, longest instructions
   2-address : the commercial compromise (destination = source)
   1-address : accumulator implied
   0-address : stack, operands implied
   Load-store: only LOAD/STORE touch memory (RISC)
   Expanding opcode: escape codes trade address fields for opcode space

One field remains unexplained: the mode field. That is the subject of the final Unit III lesson.