JK Flip-Flop
The JK flip-flop is the SR flip-flop with the forbidden state turned into a useful one: J = K = 1 makes the output toggle.
Built from SR: S = J . Q' R = K . Q
When J = K = 1:
if Q = 0 -> S = 1.1 = 1, R = 1.0 = 0 -> SET (Q becomes 1)
if Q = 1 -> S = 1.0 = 0, R = 1.1 = 1 -> RESET (Q becomes 0)
The feedback from Q and Q' guarantees S and R are never both 1.
Characteristic table
| CLK | J | K | Q(n+1) | Operation |
|---|
| ↑ | 0 | 0 | Q(n) | No change |
| ↑ | 0 | 1 | 0 | Reset |
| ↑ | 1 | 0 | 1 | Set |
| ↑ | 1 | 1 | Q(n)' | Toggle |
Characteristic equation
Q(n+1) = J.Q' + K'.Q
Derivation by K-map:
J K
00 01 11 10
+------+------+------+------+
Q=0 | 0 | 0 | 1 | 1 |
+------+------+------+------+
Q=1 | 1 | 0 | 0 | 1 |
+------+------+------+------+
Group (Q=0, J=1) -> J.Q'
Group (Q=1, K=0) -> K'.Q
Q(n+1) = J.Q' + K'.Q ✓
Excitation table
| Q(n) → Q(n+1) | J | K |
|---|
| 0 → 0 | 0 | X |
| 0 → 1 | 1 | X |
| 1 → 0 | X | 1 |
| 1 → 1 | X | 0 |
Why JK is preferred for counter design: its excitation table has an X in every row, which produces the simplest K-maps and hence the fewest gates.
State diagram
The Race Around Condition
This is one of the most frequently asked questions in COA papers.
Setup: a LEVEL-TRIGGERED (not edge-triggered) JK flip-flop,
with J = K = 1, and a clock pulse of width t(p).
Flip-flop propagation delay = t(pd).
While CLK = 1 the flip-flop is transparent, so:
t = 0 Q = 0
t = t(pd) Q toggles to 1
t = 2.t(pd) Q toggles to 0 <- because J=K=1 is STILL applied
t = 3.t(pd) Q toggles to 1
...
The output oscillates for as long as the clock stays high.
Number of toggles during one clock pulse = t(p) / t(pd)
When the clock finally falls, the final state is whichever value the
oscillation happened to land on — UNPREDICTABLE.
Definition to write in the exam: The race around condition occurs in a level-triggered JK flip-flop when J = K = 1 and the clock pulse width is greater than the propagation delay of the flip-flop. The output toggles repeatedly during the clock pulse, making the final state indeterminate.
The three cures
| Solution | How it works | Practicality |
|---|
| 1. Narrow clock pulse: make t(p) < t(pd) | Only one toggle can complete | Impractical — needs an extremely narrow, precisely controlled pulse |
| 2. Master-slave flip-flop | Two latches in series; the slave updates only after the master is isolated | Standard solution (next lesson) |
| 3. Edge triggering | The flip-flop is sensitive only at the instant of the edge, so the loop never closes | Standard in modern design |
T Flip-Flop (Toggle Flip-Flop)
Tie J and K together: T = J = K.
Characteristic table
| CLK | T | Q(n+1) | Operation |
|---|
| ↑ | 0 | Q(n) | Hold |
| ↑ | 1 | Q(n)' | Toggle |
Characteristic equation:
Q(n+1) = T.Q' + T'.Q = T ⊕ Q
Excitation table
| Q(n) → Q(n+1) | T |
|---|
| 0 → 0 | 0 |
| 0 → 1 | 1 |
| 1 → 0 | 1 |
| 1 → 1 | 0 |
(Simple rule: T = 1 when the state must change, i.e. T = Q(n) ⊕ Q(n+1).)
The T flip-flop as a frequency divider
With T tied permanently to 1, the output toggles on every clock edge:
CLK : _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
Q : ___|‾‾‾‾‾|_____|‾‾‾‾‾|____
f(Q) = f(CLK) / 2
Cascade n T flip-flops (Q of one clocking the next):
f(out) = f(CLK) / 2^n <- this IS a ripple counter.
Complete Flip-Flop Comparison Table
| Flip-flop | Inputs | Characteristic equation | Invalid state | Main use |
|---|
| SR | S, R | Q(n+1) = S + R'Q | S = R = 1 | Basic memory cell |
| D | D | Q(n+1) = D | None | Registers, pipelines |
| JK | J, K | Q(n+1) = JQ' + K'Q | None (toggles) | Counters, general sequential design |
| T | T | Q(n+1) = T ⊕ Q | None | Frequency division, binary counters |
Complete Excitation Table (memorise this — every counter design needs it)
| Q(n) → Q(n+1) | S R | J K | D | T |
|---|
| 0 → 0 | 0 X | 0 X | 0 | 0 |
| 0 → 1 | 1 0 | 1 X | 1 | 1 |
| 1 → 0 | 0 1 | X 1 | 0 | 1 |
| 1 → 1 | X 0 | X 0 | 1 | 0 |
The next lesson builds the master-slave structure that makes JK flip-flops safe to use.
