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Combinational Circuits: Multiplexers, Demultiplexers, Decoders and Encoders

Lesson 7 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

4:1 Multiplexer (MUX)

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2:1 MUX Truth Table

SY (Output)
0I₀
1I₁

Expression: Y = S'·I₀ + S·I₁

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4:1 MUX Truth Table

S₁S₀Y (Output)
00I₀
01I₁
10I₂
11I₃

Expression: Y = S₁'S₀'·I₀ + S₁'S₀·I₁ + S₁S₀'·I₂ + S₁S₀·I₃

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1:4 DEMUX Truth Table

S₁S₀Y₀Y₁Y₂Y₃
00D000
010D00
1000D0
11000D

Where D = input data.

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2:4 Decoder Truth Table

A (MSB)B (LSB)Y₀Y₁Y₂Y₃
001000
010100
100010
110001

Expressions: Y₀=A'B', Y₁=A'B, Y₂=AB', Y₃=AB

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4:2 Encoder Truth Table

I₃I₂I₁I₀A₁A₀
000100
001001
010010
100011

Priority Encoder — if multiple inputs active, highest-priority (highest index) wins.

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Decoder as Minterm Generator

A 2:4 decoder generates all 4 minterms of 2 variables. To implement any Boolean function using a decoder: connect the decoder outputs for desired minterms to an OR gate.

Example: F(A,B) = Σ(1,2) → F = Y₁ + Y₂ = A'B + AB'

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Study Deep: MUX as Universal Logic Element

A MUX can implement any Boolean function:

  • For an n-variable function, use a 2ⁿ:1 MUX
  • Connect inputs to 0 or 1 according to the truth table output
  • With (n-1) variable MUX: use Shannon expansion to reduce by 1 variable
  • Example: F(A,B,C) using a 4:1 MUX: S₁=A, S₀=B; then I₀=f(0,0,C), I₁=f(0,1,C), etc.

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Comprehensive Comparison Table

CircuitInputsOutputsSelect LinesKey FunctionUse Case
MUX 4:14 data + 2 select12Select 1 of 4Data routing, function generator
DEMUX 1:41 data + 2 select42Route to 1 of 4Data distribution
Encoder 4:24 (one-hot)2NoneBinary encodeKeyboard, interrupt priority
Decoder 2:42 binary4 (one-hot)NoneBinary decodeMemory chip select, minterm gen
Priority Enc. 4:242 + validNoneEncode highest activeInterrupt controllers
📝 Exam Tips: - MUX selects: 2ⁿ inputs → 1 output, n select lines - Decoder: n inputs → 2ⁿ outputs (exactly one output HIGH at a time) - Encoder is inverse of decoder; priority encoder resolves simultaneous active inputs - Decoder + OR gate = any combinational logic function