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Priority Interrupt Systems and DMA — Detailed Operation

Lesson 16 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

Interrupt Handling Sequence

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Interrupt Types

CategoryTypeDefinitionExamplesMaskable?
SourceHardware interruptGenerated by hardware deviceKeyboard, disk, timer, NICUsually
SourceSoftware interruptGenerated by program (INT instruction, trap)System call (INT 80h), exceptionNo
MaskMaskable (IRQ)Can be disabled by CPU (CLI instruction)Disk I/O complete, timer tickYes
MaskNon-Maskable (NMI)Cannot be disabled; highest priorityPower failure, memory parity errorNo
OriginInternalCaused by CPU itselfDivide-by-zero, overflow, page faultNo
OriginExternalFrom I/O devices outside CPUAll hardware IRQsYes

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Priority Interrupt Techniques

1. Daisy Chain (Serial Priority)

Interrupt acknowledge (INTA) signal propagates serially through all devices:

  • Device 1 (highest priority) is first in chain
  • If Device 1 requests interrupt, it captures INTA; blocks downstream devices
  • If Device 1 does NOT request, INTA propagates to Device 2, etc.
  • Disadvantage: Low-priority device can be starved; slow response for low-priority

2. Parallel Priority (Hardware Priority Encoder)

  • All devices connect to a priority encoder
  • Encoder outputs the number of highest-priority requesting device
  • CPU reads encoder output to identify interrupting device
  • Advantage: Fast; Disadvantage: Expensive hardware

3. Software Polling

  • On any interrupt, CPU polls all devices in priority order
  • First device found with active interrupt flag is serviced
  • Advantage: No extra hardware; Disadvantage: Long polling time

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Priority Arbitration Comparison

FeatureDaisy ChainParallel PrioritySoftware Polling
Response timeProportional to device positionO(1) — hardwareO(n) — software poll
Hardware costLow (one wire chain)Medium (priority encoder)Minimal
FlexibilityFixed priority orderProgrammable priorityFully programmable
FairnessUnfair (first device wins)Can implement round-robinCan implement any scheme
Max devicesLimited by chain delayLimited by encoderUnlimited

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DMA Modes Comparison

ModeDescriptionCPU Bus UsageThroughputLatencyUse Case
Burst / BlockDMA transfers entire block; CPU locked outCPU blocked during entire transferHighestHigh CPU latencyDisk block transfer, DMA for large files
Cycle StealingDMA steals one bus cycle at a time; CPU pauses briefly each cycleCPU paused 1 cycle per DMA wordMediumLow per stealStreaming video/audio
Transparent / InterleavedDMA transfers only when CPU not using bus (idle cycles)Zero CPU impactLowestUnpredictableReal-time systems where CPU must not stall

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📝 Exam Tips: - NMI (Non-Maskable Interrupt): cannot be disabled; used for critical events like power failure - IRQ (Interrupt ReQuest): maskable; can be disabled by CPU flag - ISR must save all registers it modifies (or use a dedicated ISR calling convention) - DMA HOLD/HLDA handshake: CPU grants bus to DMA controller for the transfer - Cycle stealing: DMA steals one memory cycle — CPU slows down but doesn't stop completely