The Priority Problem

   Several devices may request an interrupt at the same instant.
   The CPU must decide:

      1. WHICH device to service first  -> PRIORITY
      2. WHERE the service routine is   -> VECTORING
      3. Whether a higher-priority device may interrupt a running ISR
                                         -> NESTED INTERRUPTS

A priority interrupt system establishes a priority order among devices so that when several interrupt simultaneously, the one with the highest priority is serviced first.

   Priority is normally assigned by URGENCY and SPEED:

      Highest : power failure (NMI) — a few milliseconds to save state
                hardware error / machine check
                timer / real-time clock
                high-speed devices (disk, network) — data would be lost
                magnetic tape, printers
      Lowest  : slow character devices (keyboard, terminals)

   Rule: the FASTER the device (or the more catastrophic its data loss),
         the HIGHER its priority.

1. Software Polling

   A single interrupt line is shared. On an interrupt, the CPU runs a
   polling routine that reads each device's status in PRIORITY ORDER:

      test device 1 (highest priority)  -> if set, branch to its ISR
      test device 2                     -> if set, branch to its ISR
      test device 3
      ...

   The order of testing IS the priority.

2. Daisy-Chaining Priority (hardware serial polling)

All devices share one interrupt request line; the interrupt acknowledge (INTACK) signal is passed serially from device to device.

   Each device has:
      PI (Priority In)  and  PO (Priority Out)
      RF (interrupt Request Flip-flop)

   Logic in each device:
      PO = PI . RF'                     (pass the acknowledge along only
                                         if I am NOT requesting)
      Enable vector output = PI . RF    (place my vector on the bus only
                                         if the chain reached me AND
                                         I am requesting)

   Sequence:
      1. One or more devices assert INT (wired-OR).
      2. CPU responds with INTACK.
      3. INTACK enters device 1's PI. If device 1 is requesting, it wins
         and puts its VAD on the data bus; PO = 0 blocks everyone else.
      4. If device 1 is not requesting, PO = 1 passes INTACK to device 2,
         and so on.
      5. The CPU reads the VAD and branches to the corresponding ISR.

3. Parallel Priority Interrupt

Each device has its own bit in an interrupt register; a priority encoder determines the winner in one gate delay.

   Hardware:
      INTERRUPT REGISTER : one bit per device, set when that device requests
      MASK REGISTER      : one bit per device, allows software to DISABLE
                           individual devices
      PRIORITY ENCODER   : produces the binary code of the highest-priority
                           unmasked active request
      IST / IEN flip-flops: interrupt status and interrupt enable

   Each interrupt-register bit is ANDed with its mask bit:

      Effective request(i) = IREG(i) . MASK(i)

   These n signals feed the priority encoder.
   The encoder's output is the VECTOR ADDRESS (VAD).
   The encoder's "valid" output (IST) drives the CPU's interrupt line.

Priority encoder truth table (4 devices, I0 = highest)

   Boolean equations (from Unit II — this is the SAME circuit):

      x   = I0' . I1'                      ... using I0 highest
      y   = I0' . I1 + I0' . I2'
      IST = I0 + I1 + I2 + I3

Note the reappearance: the priority encoder of Unit II is the parallel priority interrupt circuit of Unit IV. This is a favourite examiner link.

4. The Mask Register — programmable priority

   When the ISR for device 3 begins, it writes a mask that DISABLES
   device 3 and all LOWER-priority devices, but leaves HIGHER-priority
   devices enabled.

   Effect: a higher-priority device can interrupt the running ISR
           (NESTED INTERRUPTS), but a lower-priority one cannot.

   On return, the ISR restores the previous mask.

5. Interrupt Cycle Micro-operations

   The CPU checks for interrupts at the END of every instruction cycle:

      IEN = 1  and  IST = 1  ->  enter the interrupt cycle

   Interrupt cycle:
      SP <- SP - 1
      M[SP] <- PC              (save the return address)
      M[SP-1] <- status flags  (save the condition codes)
      IEN <- 0                 (disable further interrupts)
      PC <- VAD                (branch to the service routine)

   Return from interrupt (RTI):
      restore the flags, PC <- M[SP], SP <- SP + 1, IEN <- 1

6. Vectored Interrupt

   The interrupting device supplies a VECTOR ADDRESS (VAD) that either:
      (a) IS the ISR address, or
      (b) is an INDEX into an INTERRUPT VECTOR TABLE in memory.

   Example (x86 real mode):
      Vector table starts at address 0.
      Each entry is 4 bytes.
      Interrupt number n  ->  ISR address at M[4n].

      INT 21H  ->  ISR address read from memory location 0x84 (= 4 x 0x21)

7. Comparison of the Three Priority Methods

8. Worked Question

   Q: Four devices A, B, C, D are daisy-chained in that order.
      B and D request an interrupt simultaneously. Which is serviced,
      and what are the PI/PO values?

      Device A: PI = 1 (from CPU INTACK), RF = 0  ->  PO = 1.1 = 1
      Device B: PI = 1, RF = 1  ->  PO = 1.0 = 0   <- B WINS, places its VAD
      Device C: PI = 0, RF = 0  ->  PO = 0
      Device D: PI = 0, RF = 1  ->  PO = 0, cannot place its VAD

      B is serviced. D remains pending and will win on the next
      acknowledge cycle (assuming B's request is cleared).

Summary

   Priority interrupt  = decide which simultaneous request wins
   Software polling    : test devices in order; simple, slow
   Daisy chain         : PO = PI.RF';  position determines priority
   Parallel priority   : interrupt register + mask register + priority encoder
   Mask register       : enables nested interrupts and software-set priority
   Vectored interrupt  : the device supplies the ISR address (or its index)

The highest-performance transfer method mentioned in the previous lesson still needs its own treatment — DMA, next.