Encoder
An encoder performs the inverse of a decoder: given 2^n input lines of which exactly one is active, it outputs the n-bit binary code of that line.
1. Octal-to-Binary (8-to-3) Encoder
| Active input | A2 | A1 | A0 |
|---|---|---|---|
| D0 | 0 | 0 | 0 |
| D1 | 0 | 0 | 1 |
| D2 | 0 | 1 | 0 |
| D3 | 0 | 1 | 1 |
| D4 | 1 | 0 | 0 |
| D5 | 1 | 0 | 1 |
| D6 | 1 | 1 | 0 |
| D7 | 1 | 1 | 1 |
Read each output column and OR the inputs where it is 1:
A0 = D1 + D3 + D5 + D7 (odd-numbered lines)
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7 (upper half)
Hardware: just THREE OR gates. No inverters, no AND gates.2. Decimal-to-BCD (10-to-4) Encoder
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
Used in keypad-to-BCD conversion.3. The Two Problems With a Simple Encoder
PROBLEM 1 — ambiguity when NO input is active:
All inputs 0 -> output 000
But 000 is also the code for D0 being active. Indistinguishable.
PROBLEM 2 — garbage when TWO OR MORE inputs are active:
D3 = 1 and D5 = 1 simultaneously
A2 = 1 (from D5), A1 = 1 (from D3), A0 = 1 (from both)
Output = 111 = D7 <- WRONG. Neither input was 7.Fix for problem 1: add a valid output V = D0 + D1 + ... + D7. V = 0 means "no input active", so the 000 code is only meaningful when V = 1.
Fix for problem 2: a priority encoder.
4. Priority Encoder
A priority encoder assigns a fixed priority to the inputs; when several are active it encodes the highest-priority one and ignores the rest.
4-to-2 priority encoder (D3 highest)
| D3 | D2 | D1 | D0 | A1 | A0 | V |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X | X | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | X | 0 | 1 | 1 |
| 0 | 1 | X | X | 1 | 0 | 1 |
| 1 | X | X | X | 1 | 1 | 1 |
The X entries in the input columns mean "don't care what the lower inputs are" — that is exactly what priority means.
A1 = D3 + D2
A0 = D3 + D2'.D1
V = D3 + D2 + D1 + D0
Verify D3=0, D2=1, D1=1, D0=1:
A1 = 0 + 1 = 1
A0 = 0 + 0.1 = 0 <- D2 wins over D1, code = 10 = 2 ✓
V = 18-to-3 priority encoder equations
A2 = D7 + D6 + D5 + D4
A1 = D7 + D6 + D5'D4'D3 + D5'D4'D2
A0 = D7 + D6'D5 + D6'D4'D3 + D6'D4'D2'D1
V = D7 + D6 + D5 + D4 + D3 + D2 + D1 + D0
Each term reads: "this input is active AND every higher one is not."5. Encoder vs Priority Encoder
| Basis | Simple Encoder | Priority Encoder |
|---|---|---|
| Multiple active inputs | Produces invalid output | Encodes the highest-priority one |
| Hardware | OR gates only | OR + AND + inverters |
| Valid output | Usually absent | Standard |
| Typical IC | 74148 is a priority encoder; simple encoders are rarely sold | 74148 (8-to-3), 74147 (10-to-4) |
| Cost | Low | Higher |
6. Applications
| Application | Detail |
|---|---|
| Interrupt priority (Unit IV) | Several devices raise interrupts; the priority encoder produces the vector address of the most urgent one |
| Keyboard encoding | A pressed key drives one line; the encoder produces its code. Priority handles two simultaneous key presses |
| Position sensing | One-hot shaft position → binary angle |
| Floating-point normalisation | A priority encoder finds the position of the leading 1 (leading-zero counter) |
| Bus arbitration | Choose which of several masters gets the bus |
This is precisely the parallel priority interrupt circuit you will meet in Unit IV — the same block, one unit later.
7. Complete MSI Block Comparison
| Block | In | Out | Select | Core equation |
|---|---|---|---|---|
| Multiplexer | 2^n data | 1 | n | Y = Σ m(S)·I |
| De-multiplexer | 1 data | 2^n | n | Y(i) = D·m(i) |
| Decoder | n code | 2^n | — (enable) | Y(i) = m(i) |
| Encoder | 2^n one-hot | n code | — | A(j) = OR of lines with bit j set |
| Priority encoder | 2^n | n + valid | — | Highest active input wins |
Combinational circuits can compute, route and select — but they cannot remember. The next lesson introduces the feedback loop that gives a circuit memory.