Master-Slave Flip-Flop
A master-slave flip-flop cascades two level-triggered flip-flops driven by complementary clocks, so that at no instant is the whole device transparent from input to output. This eliminates the race around condition.
How It Works — the two half-cycles
CLK = 1 (clock HIGH):
MASTER is ENABLED -> it accepts J and K, and its output Qm changes.
SLAVE is DISABLED -> Q holds the old value.
The external output Q does NOT change, so the feedback into
the master's AND gates is FROZEN -> the master can toggle at most ONCE.
CLK = 0 (clock LOW):
MASTER is DISABLED -> Qm is frozen; input changes are ignored.
SLAVE is ENABLED -> Q copies Qm.
Net effect: the input is sampled while the clock is HIGH,
and transferred to the output on the FALLING edge.
-> This is a NEGATIVE-edge-triggered device. Timing:
CLK _|‾‾‾‾‾‾|______|‾‾‾‾‾‾|______
^master ^slave
samples transfers
J=K=1, initial Q = 0:
Qm ______|‾‾‾‾‾‾‾‾‾‾‾‾|_________ (toggles once per HIGH period)
Q _____________|‾‾‾‾‾‾‾‾‾‾‾‾|____ (updates on the FALLING edge)Why the Race Disappears
In a plain level-triggered JK, the loop is:
Q changes -> feedback changes S,R -> Q changes again -> ...
(all within ONE clock-high period)
In master-slave, the loop is BROKEN:
while CLK = 1 the slave is closed, so Q is constant,
so the feedback into the master never changes,
so the master toggles AT MOST ONCE.The "1s Catching" Problem
Master-slave flip-flops have their own weakness, worth one mark in most papers:
Suppose J = 0, K = 0 at the start of the clock-high period,
but a NOISE SPIKE puts J = 1 briefly in the middle of that period.
The master captures the 1 and cannot un-capture it (its own feedback
holds it). At the falling edge, that spurious 1 is transferred to Q.
-> "1s catching" / "0s catching".
-> Cure: use a TRUE EDGE-TRIGGERED flip-flop (6-gate structure),
which samples only during the few picoseconds at the edge.Master-Slave with D Input
Master: D latch clocked by CLK
Slave : D latch clocked by CLK'
Result: a negative-edge-triggered D flip-flop with
Q(n+1) = D sampled at the falling edge.Types of Triggering — the full picture
| Type | Symbol on C input | Q updates when |
|---|---|---|
| Positive level | plain (no triangle) | CLK = 1 (transparent) |
| Negative level | bubble only | CLK = 0 |
| Positive edge | triangle | CLK 0 → 1 |
| Negative edge | triangle + bubble | CLK 1 → 0 |
| Master-slave (pulse) | usually shown as negative edge | at the trailing edge |
Complete Timing Analysis Example
A master-slave JK flip-flop, initially Q = 0.
Inputs over five clock pulses:
Pulse | J | K | Master action (CLK=1) | Q after falling edge
------+---+---+-----------------------+---------------------
1 | 1 | 0 | Qm -> 1 (set) | Q = 1
2 | 0 | 0 | Qm holds = 1 | Q = 1
3 | 0 | 1 | Qm -> 0 (reset) | Q = 0
4 | 1 | 1 | Qm -> 1 (toggle) | Q = 1
5 | 1 | 1 | Qm -> 0 (toggle) | Q = 0
Note: each toggle happens exactly ONCE per clock, never repeatedly.Setup and Hold in a Master-Slave Device
The inputs must be stable:
- throughout the master's sampling window (the clock-high period),
or at minimum for t(su) before the falling edge and t(h) after it.
Violating this is what allows 1s catching to occur.Summary — Clocked Flip-Flop Concepts
| Concept | Definition |
|---|---|
| Clocked flip-flop | State changes only when the clock permits it |
| Race around | Repeated toggling of a level-triggered JK when J = K = 1 and t(pulse) > t(pd) |
| Master-slave | Two cascaded latches on complementary clocks; input sampled on one level, output updated on the edge |
| 1s catching | A brief input glitch captured by the master and passed to the output |
| Edge triggering | Sampling confined to the clock transition — the modern standard |
| Preset / Clear | Asynchronous overrides, independent of the clock |
With flip-flops understood, the next lesson answers a favourite exam question: how do you convert one type of flip-flop into another?