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Unit IV Overview: I/O Organization and Memory Hierarchy

Lesson 14 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

I/O and Memory Organization Overview

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Memory Hierarchy (8 Levels)

LevelTypeTechnologySpeedCost/bitTypical CapacityVolatile?
1CPU RegistersFlip-flops~0.3 nsVery High32–256 bytesYes
2L1 CacheSRAM~1 nsHigh16–64 KBYes
3L2 CacheSRAM~3–5 nsHigh256 KB–2 MBYes
4L3 CacheSRAM~10–30 nsMedium-High4–64 MBYes
5Main MemoryDRAM~50–100 nsMedium4–64 GBYes
6SSD/FlashNAND Flash~100 µsLow256 GB–4 TBNo
7HDDMagnetic disk~5–10 msVery Low1–20 TBNo
8Tape/OpticalMagnetic/OpticalsecondsExtremely LowExabytesNo

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Principle of Locality

The memory hierarchy works because of two observed properties of program execution:

Temporal Locality: If a memory location is accessed, it is likely to be accessed again soon.

  • Example: Loop variable i is accessed every iteration
  • Solution: Keep recently used data in cache

Spatial Locality: If a location is accessed, nearby locations are likely accessed soon.

  • Example: Sequential array traversal, program instructions execute in order
  • Solution: Cache fetches entire cache lines (typically 64 bytes) not just one word

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Study Deep: The Cost-Speed-Capacity Triangle

The fundamental trade-off in memory design — you can only optimize two of three:

PropertyFast AND SmallFast AND LargeCheap AND Large
ExampleCPU registersSRAM (would be expensive)Hard disk drive
ProblemNot enough capacityProhibitively expensiveFar too slow
SolutionUse in hierarchyUse cache (small SRAM)Use HDD as last resort

The memory hierarchy is the engineering solution: use fast-expensive memory for frequently accessed data, slow-cheap memory for bulk storage, and rely on locality to make this effective.

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Unit IV Lessons Overview

LessonTitleKey Topics
Lesson 15I/O Interfaces and Peripheral DevicesProgrammed I/O, Interrupt I/O, DMA, Asynchronous transfer
Lesson 16Priority Interrupts and DMAInterrupt handling, Priority schemes, DMA modes
Lesson 17Memory OrganizationCache, Virtual memory, SRAM/DRAM, Replacement policies
📝 Exam Tip: The memory hierarchy is a classic exam topic. Remember the access time order: Registers (~0.3 ns) → L1 (~1 ns) → L2 (~5 ns) → L3 (~20 ns) → RAM (~60 ns) → SSD (~100 µs) → HDD (~10 ms). Each level is 5–100× slower than the previous.