The Instruction Cycle

The CPU repeats one loop forever. Every phase is a sequence of micro-operations timed by a sequence counter (SC) whose outputs are decoded into timing signals T0, T1, T2, …

1. The Timing Signals

   A 4-bit sequence counter SC feeds a 4-to-16 decoder producing
   T0, T1, T2, ... T15.

   SC is INCREMENTED after every clock pulse, and CLEARED (SC <- 0)
   at the end of each instruction to restart at T0.

   This is exactly the counter + decoder of Unit II.

2. Fetch and Decode — the micro-operations

   T0:  AR <- PC
   T1:  IR <- M[AR],  PC <- PC + 1
   T2:  D0..D7 <- decode IR(12-14),  AR <- IR(0-11),  I <- IR(15)

What happens at each step

   T0: The address of the next instruction (in PC) is copied to AR,
       because ONLY AR can address memory.
       Control: S2S1S0 = 010 (PC onto the bus), LD(AR) = 1

   T1: The memory word at that address is read into IR.
       Simultaneously PC is incremented so it already points at the
       NEXT instruction — this is why a branch instruction must
       OVERWRITE PC rather than adjust it.
       Control: S2S1S0 = 111 (memory onto the bus), READ = 1,
                LD(IR) = 1, INR(PC) = 1

   T2: The 3 opcode bits are decoded into D0..D7 (one-hot).
       The 12 address bits move into AR.
       Bit 15 is stored in the I flip-flop.
       Control: S2S1S0 = 101 (IR onto the bus), LD(AR) = 1

Note that fetch takes the same three cycles for every instruction. Only the execute phase varies in length.

3. Determining the Instruction Type at T3

   At T3 the control unit branches four ways:

   D7' I  T3:  AR <- M[AR]         indirect memory-reference: read the pointer
   D7' I' T3:  (nothing)           direct memory-reference: AR already correct
   D7  I' T3:  execute a REGISTER-REFERENCE instruction, SC <- 0
   D7  I  T3:  execute an INPUT-OUTPUT instruction, SC <- 0

   D7 = 1 means the opcode was 111.

4. Execute Phase — the seven memory-reference instructions

AND (D0)

   D0 T4:  DR <- M[AR]
   D0 T5:  AC <- AC ^ DR,  SC <- 0

ADD (D1)

   D1 T4:  DR <- M[AR]
   D1 T5:  AC <- AC + DR,  E <- Cout,  SC <- 0

LDA — load AC (D2)

   D2 T4:  DR <- M[AR]
   D2 T5:  AC <- DR,  SC <- 0

STA — store AC (D3)

   D3 T4:  M[AR] <- AC,  SC <- 0        (only ONE extra cycle)

BUN — branch unconditionally (D4)

   D4 T4:  PC <- AR,  SC <- 0

   The effective address simply replaces the program counter.

BSA — branch and save return address (D5)

   D5 T4:  M[AR] <- PC,  AR <- AR + 1
   D5 T5:  PC <- AR,  SC <- 0

   This is a SUBROUTINE CALL:
      the return address (already incremented PC) is stored at the
      subroutine's first location, and execution begins at AR + 1.
      Return is achieved with an INDIRECT BUN through that location.

   Example: BSA 135 executed while PC = 021

      M[135] <- 021          (save the return address)
      PC     <- 136          (start executing the subroutine body)

      The subroutine ends with:   BUN I 135
      which loads PC with M[135] = 021  -> returns to the caller.  ✓

ISZ — increment and skip if zero (D6)

   D6 T4:  DR <- M[AR]
   D6 T5:  DR <- DR + 1
   D6 T6:  M[AR] <- DR,  if (DR = 0) then (PC <- PC + 1),  SC <- 0

   Used for loop counters: store a negative count, increment it each
   pass, and when it reaches zero skip the branch that repeats the loop.

5. Register-Reference Instructions (executed entirely at T3)

   Let r = D7 I' T3   and  B(i) = IR(i)

   r:        SC <- 0                        (common to all)
   r B11:    AC <- 0                        CLA
   r B10:    E  <- 0                        CLE
   r B9 :    AC <- AC'                      CMA
   r B8 :    E  <- E'                       CME
   r B7 :    AC <- shr AC, AC(15) <- E, E <- AC(0)    CIR
   r B6 :    AC <- shl AC, AC(0)  <- E, E <- AC(15)   CIL
   r B5 :    AC <- AC + 1                   INC
   r B4 :    if (AC(15) = 0) then PC <- PC + 1        SPA
   r B3 :    if (AC(15) = 1) then PC <- PC + 1        SNA
   r B2 :    if (AC = 0)     then PC <- PC + 1        SZA
   r B1 :    if (E = 0)      then PC <- PC + 1        SZE
   r B0 :    S <- 0  (halt)                 HLT

Each of these needs only one clock cycle — no memory access is required.

6. Complete Flowchart of the Instruction Cycle

   SC <- 0
     |
   T0:  AR <- PC
   T1:  IR <- M[AR], PC <- PC + 1
   T2:  Decode, AR <- IR(0-11), I <- IR(15)
     |
     +-- D7 = 1, I = 0  ->  T3: register-reference, SC <- 0
     +-- D7 = 1, I = 1  ->  T3: I/O instruction,    SC <- 0
     +-- D7 = 0, I = 1  ->  T3: AR <- M[AR]  -> T4...
     +-- D7 = 0, I = 0  ->  T3: nothing      -> T4...
     |
   T4..T6:  execute the memory-reference instruction, SC <- 0
     |
   back to T0

7. Instruction Cycle Timing Summary

8. The Interrupt Cycle

   The interrupt flip-flop R is set when an I/O flag is on and IEN = 1.

   R T0:  AR <- 0,  TR <- PC
   R T1:  M[AR] <- TR,  PC <- 0
   R T2:  PC <- PC + 1,  IEN <- 0,  R <- 0,  SC <- 0

   Effect: the return address is stored at memory location 0, and
   execution continues at location 1, where the service routine's
   branch instruction lives.

Now that instructions execute, the remaining Unit III lessons look at how they are organised: register files, stacks, formats and addressing modes.