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Instruction Codes, Computer Registers and The Instruction Cycle

Lesson 12 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

Instruction Cycle Flowchart

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Instruction Code Structure

An instruction word consists of:

  • Opcode (Operation Code): specifies the operation (ADD, LOAD, JUMP, etc.)
  • Operand/Address field: specifies the data source/destination

Example (16-bit instruction, 4-bit opcode + 12-bit address):

[15..12] Opcode (4 bits = 16 operations)
[11..0]  Address field (12 bits = 4096 memory locations)

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Instruction Format Comparison

FormatOpcodeAddress FieldsExample (A = B + C)ProsCons
3-addressShort3 (src1, src2, dst)ADD A,B,CSingle instructionLong instruction word
2-addressMedium2 (src, dst)MOV A,B; ADD A,CFewer instructions than 1-addrOne operand overwritten
1-addressLong1 (operand)LOAD B; ADD C; STORE ASimple hardware (accumulator)Many instructions needed
0-address (stack)Longest0 (implicit stack)PUSH B; PUSH C; ADD; POP ANo address decodingStack management overhead

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FETCH Cycle RTL (Same for all instructions)

TimingRTLDescription
T₀MAR ← PCCopy PC (instruction address) to MAR
T₁MDR ← M[MAR], PC ← PC+1Fetch instruction byte(s); increment PC
T₂IR ← MDRLoad fetched instruction into IR

After T₂: decode IR opcode to determine which execute sub-sequence to run.

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EXECUTE Cycle RTL — ADD Instruction (ADD M[X])

TimingConditionRTLDescription
T₃D0=ADDMAR ← IR[0:11]Get operand address from instruction
T₄D0=ADDMDR ← M[MAR]Read operand from memory
T₅D0=ADDAC ← AC + MDR, SC ← 0Add to accumulator; reset sequence counter

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General Register Organization

Modern CPUs have a register file — a set of n general-purpose registers (GPRs):

ComponentDescription
Register file8–32 GPRs; any register can hold data or address
Input multiplexersSelect which two registers go to ALU
ALUPerforms operation on two selected registers
Output demultiplexerRoutes result to destination register

This allows R-type instructions: OP Rd, Rs1, Rs2 (all operands in registers — no memory access needed).

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Study Deep: RISC vs CISC Philosophy

RISC (Reduced Instruction Set Computer): Few, simple instructions. Each executes in 1 clock cycle. Load/Store architecture — memory accessed only by LOAD/STORE, all other operations use registers.

CISC (Complex Instruction Set Computer): Many complex instructions. One instruction can do a memory-to-memory operation. Designed for code density; requires complex control unit (microprogrammed).

RISC vs CISC Comparison

FeatureRISCCISC
Instruction countLarge (many simple instructions)Small (few complex instructions)
Instruction complexityFixed-length, simpleVariable-length, complex
Clocks per instruction~1 (pipelined)1–20+
Register fileLarge (32+ GPRs)Small (8–16)
Memory accessLOAD/STORE onlyMany instructions access memory
Control unitHardwired (fast)Microprogrammed (flexible)
Code densityLower (more instructions)Higher (fewer instructions)
ExamplesRISC-V, ARM, MIPS, SPARCx86, x86-64, VAX
📝 Exam Tips: - Fetch cycle is always T0:MAR←PC; T1:MDR←M[MAR],PC←PC+1; T2:IR←MDR — memorize this! - 1-address machine: uses accumulator as implicit second operand - Stack machine (0-address): uses PUSH/POP — operands are on stack, no address needed in instruction - RISC: simple instructions, many registers; CISC: complex instructions, few registers