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Register Transfer Language, Bus Structure and Memory Transfer

Lesson 11 of 17 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

Single Bus Structure

A single-bus architecture: only one transfer can occur per clock cycle. 3-state buffers (tri-state) allow multiple registers to share the bus — only one drives the bus at a time (others float to high-impedance Z).

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RTL Notation Conventions

NotationMeaningRTL Example
R ← 0Clear registerAC ← 0
Ri ← RjCopy registerR1 ← R2
Ri ← Ri + RjArithmetic addAC ← AC + DR
Ri ← Ri ⊕ RjLogical XORR1 ← R1 ⊕ R2
Ri ← shl(Ri)Shift leftAC ← shl(AC)
Ri ← M[Rj]Memory readDR ← M[AR]
M[Ri] ← RjMemory writeM[AR] ← DR
PC ← PC + 1Increment PCPC ← PC + 1

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Four Types of Micro-Operations

1. Register Transfer Micro-Operations

Direct copy of data between registers:

  • R1 ← R2 — copy R2 to R1
  • [R1, R2] ← [R3, R4] — simultaneous transfers

2. Arithmetic Micro-Operations

OperationRTLDescription
AddR1 ← R2 + R3Binary addition
SubtractR1 ← R2 − R32's complement subtraction
IncrementR1 ← R1 + 1Add 1
DecrementR1 ← R1 − 1Subtract 1
NegateR1 ← R1' + 12's complement negate
TransferR1 ← R2Unmodified copy

3. Logic Micro-Operations

OperationRTLDescription
ANDR1 ← R1 ∧ R2Bitwise AND (masking)
ORR1 ← R1 ∨ R2Bitwise OR (setting bits)
XORR1 ← R1 ⊕ R2Bitwise XOR (flipping bits)
ComplementR1 ← R1'Bitwise NOT (1's complement)
ClearR1 ← R1 ⊕ R1XOR with self = 0

4. Shift Micro-Operations

TypeRTLDescription
Logical shift leftR1 ← shl(R1)Shift left; 0 enters LSB
Logical shift rightR1 ← shr(R1)Shift right; 0 enters MSB
Circular (rotate) leftR1 ← cil(R1)MSB goes to LSB
Circular (rotate) rightR1 ← cir(R1)LSB goes to MSB
Arithmetic shift rightR1 ← ashr(R1)Sign bit replicated (preserves sign)

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Memory Transfer Operations

OperationRTLDescriptionAddress Source
ReadDR ← M[AR]Load data from address in AR into DRAR holds address
WriteM[AR] ← DRStore data from DR to address in ARAR holds address
Fetch instructionMDR ← M[MAR], PC ← PC+1Fetch + auto-increment PCMAR from PC

Memory transfer timing: involves clock cycles for address setup, memory access, and data latch.

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📝 Exam Tips: - Micro-operations are the most primitive actions a CPU can perform in one clock cycle - A single assembly instruction may require 5–10 micro-operations - Arithmetic shift right preserves the sign bit (important for signed integers) - Single-bus: cheap but only 1 register can drive bus per cycle → slower than multi-bus