Register Transfer Language (RTL)

RTL is a symbolic notation for describing what a digital system does in terms of registers and the operations performed on the data stored in them. It is the language in which every CPU in Unit III is specified.

   A digital system at the register-transfer level is described by:
      1. The set of registers it contains
      2. The micro-operations performed on their contents
      3. The control that sequences those micro-operations

1. Micro-operation

A micro-operation is an elementary operation performed on the data stored in registers, completed in one clock pulse.

2. Register Notation

   R1              a register named R1
   R1[0-7]         bits 0 through 7 of R1
   R2[L]           the low-order byte of R2
   PC(H), PC(L)    high and low bytes of the program counter

   Registers are drawn as rectangles with the name inside; the bit
   numbering is usually written above, with bit 0 at the RIGHT (LSB).

3. The Register Transfer Statement

   R2 <- R1

   Meaning: the contents of R1 are COPIED into R2.
            R1 is UNCHANGED (the transfer is non-destructive to the source).
            The transfer happens on ONE clock edge, in PARALLEL for all bits.

Conditional transfer

   if (P = 1) then (R2 <- R1)

   is written as:      P: R2 <- R1

   P is a CONTROL FUNCTION — a Boolean variable produced by the control unit.
   The colon terminates the control function.

Simultaneous transfers

   T: R2 <- R1, R1 <- R2

   Both transfers occur on the SAME clock edge -> this SWAPS the two registers.
   It works only because the flip-flop inputs are sampled before the
   outputs change (edge triggering, from Unit II).

   The comma separates micro-operations that happen at the same time.

4. Hardware Implementation of a Register Transfer

   P: R2 <- R1

   Hardware:
      - n data lines from R1 to R2 (one per bit)
      - the control signal P is connected to the LOAD input of R2
      - the common clock drives both registers

   Timing:
      P is generated during one clock cycle;
      the transfer occurs at the NEXT rising edge while P = 1.

Important: the clock is not included in the RTL statement. Every RTL statement is implicitly synchronised to the clock; the control function decides whether the transfer happens, never when the clock ticks.

5. Basic Symbols of RTL

6. Arithmetic Micro-operations

   Subtraction is NOT a separate micro-operation in hardware:

      R3 <- R1 - R2   is implemented as   R3 <- R1 + R2' + 1

   (exactly the parallel adder/subtractor of Unit I)

Hardware note: multiplication and division are not micro-operations. They are sequences of add-and-shift or subtract-and-shift micro-operations executed over many clock cycles.

7. Logic Micro-operations

Logic micro-operations are bitwise operations on register contents.

   Note the deliberate symbol split:
      +  means ARITHMETIC ADD in a micro-operation
      v  means LOGICAL OR

   P + Q: R1 <- R2, R3 <- R4
      Here the "+" between P and Q is a LOGICAL OR (it is in the control
      function, before the colon).
   R1 <- R2 + R3
      Here "+" is arithmetic addition (it is after the colon).

The four useful applications of logic micro-operations

   Let R1 = 1010 1101 (data), R2 = the mask.

   1. SELECTIVE SET     : R1 <- R1 v R2      sets bits where R2 = 1
      R2 = 0000 1111  ->  R1 = 1010 1111

   2. SELECTIVE CLEAR   : R1 <- R1 ^ R2'     clears bits where R2 = 1
      R2 = 0000 1111  ->  R1 = 1010 0000

   3. SELECTIVE COMPLEMENT : R1 <- R1 (XOR) R2   flips bits where R2 = 1
      R2 = 0000 1111  ->  R1 = 1010 0010

   4. MASK (AND)        : R1 <- R1 ^ R2      keeps bits where R2 = 1
      R2 = 1111 0000  ->  R1 = 1010 0000

   5. INSERT            : mask out the field, then OR in the new value
      R1 <- (R1 ^ mask') v newfield

   6. CLEAR             : R1 <- R1 (XOR) R2  gives all 0s when R1 = R2
      (a fast equality test)

8. Shift Micro-operations

   R = 1011 0101

   shl  ->  0110 1010      (x2, but the MSB 1 is lost)
   shr  ->  0101 1010      (/2 unsigned)
   cil  ->  0110 1011      (the lost MSB comes back at the LSB)
   cir  ->  1101 1010
   ashr ->  1101 1010      (sign bit 1 is copied)  -> correct /2 for signed
   ashl ->  0110 1010      (overflow if the sign bit changes)

   Arithmetic shift left OVERFLOW rule:
      overflow if  R(n-1)  XOR  R(n-2) = 1   BEFORE the shift
      (i.e. the sign bit is about to change)

9. Putting It Together — a complete RTL description

   A small system: swap R1 and R2 if P = 1, else add them into R3.

      P:   R1 <- R2, R2 <- R1
      P':  R3 <- R1 + R2

   A memory read into the data register:

      T: DR <- M[AR]

   Increment the program counter:

      T: PC <- PC + 1

Summary

The next lesson answers the practical question RTL raises: with dozens of registers, how does data physically move between any pair of them?