Direct Memory Access
DMA is a transfer technique in which a dedicated controller moves data directly between an I/O device and memory, without routing it through the CPU.
Without DMA: Device -> CPU register -> Memory (2 bus cycles/word,
CPU involved per word)
With DMA: Device -> Memory (1 bus cycle/word,
CPU not involved)
1. Bus Request and Bus Grant
Two control lines connect the DMA controller to the CPU:
BR (Bus Request) : the DMA controller asks for control of the buses.
BG (Bus Grant) : the CPU replies that it has FLOATED its bus drivers
(address, data and control lines go to high impedance).
Sequence:
1. DMA controller asserts BR.
2. CPU finishes the current bus cycle.
3. CPU floats its address, data, RD and WR lines and asserts BG.
4. DMA controller now DRIVES the buses and performs the transfer.
5. DMA controller deasserts BR; the CPU deasserts BG and resumes.
Important: the CPU does not stop executing — it only stops using the bus. Instructions already in the pipeline or operating on cache/registers continue normally. This is why DMA is described as transparent rather than blocking.
2. Registers Inside the DMA Controller
| Register | Purpose |
|---|
| Address register | Holds the current memory address; incremented after each word |
| Word count register | Number of words remaining; decremented after each word; when it reaches 0 the transfer ends |
| Control register | Direction (read/write), transfer mode, auto-initialise |
| Status register | Transfer complete, error flags |
DMA initialisation by the CPU (via ordinary I/O writes):
1. Write the STARTING MEMORY ADDRESS into the address register.
2. Write the WORD COUNT into the count register.
3. Write the CONTROL word: direction (memory-read = output to device,
memory-write = input from device), and the transfer mode.
4. Set the DMA START bit.
The CPU then goes back to running programs.
End of transfer:
When the word count reaches 0, the DMA controller
- stops requesting the bus,
- sets its "done" status bit,
- raises an INTERRUPT to tell the CPU the block is complete.
3. The Three DMA Transfer Modes
(a) Burst / Block transfer mode
The DMA controller keeps the bus for the WHOLE block.
+ Fastest possible transfer of the block
- The CPU is completely bus-starved for the duration
Used for: magnetic disk transfers, where the data stream cannot be
interrupted once the head is over the sector.
(b) Cycle stealing mode
The DMA controller transfers ONE word, then releases the bus,
then requests it again for the next word.
+ The CPU gets bus cycles in between -> the system stays responsive
- Slower overall, more BR/BG overhead
Used for: most general-purpose DMA. The name comes from "stealing"
one memory cycle from the CPU at a time.
(c) Transparent / hidden mode
The DMA controller monitors the CPU and transfers ONLY during cycles
in which the CPU is not using the bus (e.g. internal ALU operations,
or cache hits).
+ ZERO impact on CPU performance
- Slowest; requires the DMA controller to decode CPU states
| Mode | CPU impact | Speed | Use |
|---|
| Burst | High (CPU halted from bus) | Fastest | Disk block transfer |
| Cycle stealing | Moderate | Medium | General purpose |
| Transparent | None | Slowest | Background transfers |
4. DMA Transfer Sequence — complete
1. The device (e.g. a disk) has data ready and asserts DMA REQUEST.
2. The DMA controller asserts BR to the CPU.
3. The CPU completes the current bus cycle and asserts BG,
floating its bus drivers.
4. The DMA controller places the memory address on the address bus,
asserts DMA ACKNOWLEDGE to the device,
and asserts the memory WRITE (for input) or READ (for output) line.
5. One word moves DIRECTLY between the device and memory.
6. The DMA controller increments the address register and
decrements the word count register.
7. If the count is not zero -> repeat from step 4 (burst) or
release the bus and repeat from step 2 (cycle stealing).
8. If the count is zero -> deassert BR, interrupt the CPU.
5. Worked Numericals
Q1: A DMA controller transfers 32-bit words to memory at 400 ns per word.
The CPU normally fetches and executes instructions at 1 million
instructions per second. By how much is the CPU slowed if the DMA
operates in cycle-stealing mode and transfers 5 MB?
Words to transfer = 5 MB / 4 bytes = 1,310,720 words
Time for transfer = 1,310,720 x 400 ns = 0.524 s
During this time the CPU loses one memory cycle per word.
If a CPU instruction takes 1 microsecond and each stolen cycle
is 400 ns, the CPU is slowed by 400ns per word.
Total CPU time lost = 0.524 s.
Q2: A disk transfers at 2 MB/s using 4-byte words. What percentage
of a 1 GHz CPU's memory bandwidth does DMA consume, if each
memory cycle takes 10 ns?
Words per second = 2 MB / 4 = 524,288 words/s
Bus time per second = 524,288 x 10 ns = 5.24 ms
Percentage = 5.24 ms / 1000 ms = 0.52 %
Q3: A DMA controller is initialised with address = 2000H and
word count = 100H, in memory-write (input) mode.
After 40H words are transferred, what do the registers hold?
Address register = 2000H + 40H = 2040H (assuming 1 address/word)
Word count = 100H - 40H = 0C0H
6. Advantages and Disadvantages
| Advantages | Disadvantages |
|---|
| Very high transfer rate | Extra hardware (the DMA controller) |
| CPU is free for other work | Cache coherency problems — memory can change behind the cache's back |
| One bus cycle per word instead of two | Bus contention slows the CPU |
| One interrupt per block, not per word | More complex programming and debugging |
| Essential for disk, network, video | A faulty DMA program can corrupt any memory (a security concern — hence the IOMMU) |
7. Cache Coherency with DMA
Problem: DMA writes new data into main memory. The CPU's cache still
holds the OLD copy of that memory -> the CPU reads stale data.
Solutions:
1. Mark the DMA buffer region as NON-CACHEABLE.
2. FLUSH / INVALIDATE the affected cache lines before/after DMA.
3. BUS SNOOPING — the cache watches the bus and invalidates any
line whose address the DMA controller writes.
8. DMA and the Memory Hierarchy
Modern systems extend DMA into:
Bus mastering : the device itself contains its own DMA engine
(every PCIe card does this)
Scatter-gather : one DMA operation follows a LIST of
address/length descriptors, so a fragmented
buffer can be filled in one go
IOMMU : an MMU for devices — translates and restricts
the addresses a device may access
Summary
DMA : device <-> memory transfer with no CPU per-word involvement
BR / BG : bus request and bus grant handshake with the CPU
Registers : address (increments), word count (decrements), control, status
Modes : burst (fastest), cycle stealing (balanced), transparent (invisible)
Ends with : one interrupt when the word count reaches zero
I/O organization is complete. The remaining Unit IV lessons turn to the other half of the syllabus: memory organization.
