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Unit III Overview: Data Transfer Operations and Computer Organization — Computer Organization and Architecture Notes

Fetch-Decode-Execute Cycle

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RTL Notation Reference

Symbol	Meaning	Example
←	Transfer (assign)	R1 ← R2 (copy R2 into R1)
M[addr]	Memory at address	DR ← M[AR] (read memory)
R[n]	Register n	R[3] ← 0
Br[x:y]	Bits x to y of register B	IR[0:11] (operand field)
P: statement	Conditional transfer	(P: T2): MAR ← IR[addr]
[R1, R2] ← f	Simultaneous transfers	[MAR, R1] ← R2, 0
+ - * ⊕	Arithmetic and logic ops	AC ← AC + DR

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Computer Registers

Register	Full Name	Typical Size	Role
PC	Program Counter	16–64 bit	Holds address of next instruction
MAR	Memory Address Register	16–64 bit	Address bus to memory
MDR/MBR	Memory Data/Buffer Register	8–64 bit	Data bus to/from memory
IR	Instruction Register	16–32 bit	Currently executing instruction
TR	Temporary Register	8–64 bit	Temporary storage during micro-ops
INPR	Input Register	8 bit	Receives character from input device
OUTR	Output Register	8 bit	Sends character to output device
AC	Accumulator	8–64 bit	Primary ALU result register

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Unit III Lessons Overview

Lesson	Title	Key Topics
Lesson 11	RTL and Bus Structure	RTL notation; micro-operations; single-bus; memory transfer
Lesson 12	Instruction Cycle	Instruction formats; fetch-execute RTL; RISC vs CISC
Lesson 13	Addressing Modes	Stack; 10 addressing modes; memory access counts

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Micro-Operations for ADD Instruction

The RTL sequence for executing ADD M[addr] (add memory operand to accumulator):

Clock	RTL Notation	Description
T0	MAR ← PC	Load PC into MAR (address of instruction)
T1	MDR ← M[MAR], PC ← PC+1	Fetch instruction from memory; increment PC
T2	IR ← MDR	Load instruction into IR
T3	MAR ← IR[0:11]	Load operand address from instruction
T4	MDR ← M[MAR]	Fetch operand from memory
T5	AC ← AC + MDR	Add operand to accumulator

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Study Deep: Hardwired vs Microprogrammed Control Unit

Hardwired CU: Logic gates and flip-flops implement the state machine directly. Fast (combinational logic) but difficult to modify. Used in RISC processors.

Microprogrammed CU: Each instruction is decoded into a sequence of micro-instructions stored in a control memory (microprogram). Flexible — change microprogram to change instruction behavior. Used in CISC processors (x86).

📝 Exam Tip: The fetch cycle is the same for ALL instructions: T0: MAR←PC; T1: MDR←M[MAR], PC←PC+1; T2: IR←MDR. Only the execute phase differs per instruction. This 3-step fetch is guaranteed exam material.