Building the Hardware for Micro-operations
The previous lessons named the micro-operations. This lesson builds the circuits that perform them — culminating in a complete Arithmetic Logic Shift Unit, which is the computational core of every CPU.
1. The Arithmetic Circuit
One parallel adder plus a small MUX on the B input performs eight different arithmetic micro-operations.
Each stage: a full adder with inputs A(i), Y(i), and carry.
Y(i) is chosen by a 4-to-1 MUX with select lines S1 S0:
S1 S0 = 00 -> Y = B
S1 S0 = 01 -> Y = B'
S1 S0 = 10 -> Y = 0
S1 S0 = 11 -> Y = 1| S1 | S0 | Cin | Y | Output D = A + Y + Cin | Micro-operation |
|---|---|---|---|---|---|
| 0 | 0 | 0 | B | D = A + B | Add |
| 0 | 0 | 1 | B | D = A + B + 1 | Add with carry |
| 0 | 1 | 0 | B' | D = A + B' | Subtract with borrow |
| 0 | 1 | 1 | B' | D = A + B' + 1 | Subtract (A − B) |
| 1 | 0 | 0 | 0 | D = A | Transfer A |
| 1 | 0 | 1 | 0 | D = A + 1 | Increment A |
| 1 | 1 | 0 | 1 (all 1s) | D = A − 1 | Decrement A |
| 1 | 1 | 1 | 1 (all 1s) | D = A | Transfer A |
Why S1S0 = 11 with Cin = 0 gives A - 1:
All 1s in 2's complement is -1.
A + (-1) + 0 = A - 1 ✓
Why S1S0 = 11 with Cin = 1 gives A:
A + (-1) + 1 = A ✓Result: one 4-bit adder, four MUXes and two control lines give you eight arithmetic operations. This economy is the whole point of the design.
2. The Logic Circuit
For each bit position, one 4-to-1 MUX selects among four gate outputs:
S1 S0 = 00 -> E = A ^ B (AND)
S1 S0 = 01 -> E = A v B (OR)
S1 S0 = 10 -> E = A ⊕ B (XOR)
S1 S0 = 11 -> E = A' (Complement)
These four are enough: any of the 16 possible two-variable logic
functions can be produced by a sequence of these operations.All 16 logic micro-operations (for completeness)
| Boolean function | Micro-operation | Name |
|---|---|---|
| F = 0 | F ← 0 | Clear |
| F = xy | F ← A ∧ B | AND |
| F = xy' | F ← A ∧ B' | |
| F = x | F ← A | Transfer A |
| F = x'y | F ← A' ∧ B | |
| F = y | F ← B | Transfer B |
| F = x ⊕ y | F ← A ⊕ B | XOR |
| F = x + y | F ← A ∨ B | OR |
| F = (x+y)' | F ← (A ∨ B)' | NOR |
| F = (x⊕y)' | F ← (A ⊕ B)' | XNOR |
| F = y' | F ← B' | Complement B |
| F = x + y' | F ← A ∨ B' | |
| F = x' | F ← A' | Complement A |
| F = x' + y | F ← A' ∨ B | |
| F = (xy)' | F ← (A ∧ B)' | NAND |
| F = 1 | F ← all 1s | Set to all 1s |
3. The Shift Unit
A combinational shifter is built from one MUX per output bit:
H(i) = shift-right input: A(i+1) with IR entering the MSB
H(i) = shift-left input: A(i-1) with IL entering the LSB
Select line H (or S):
S = 0 -> shift right
S = 1 -> shift left
Serial inputs IR and IL determine the shift TYPE:
logical : 0 enters
circular : the bit that fell off the other end enters
arithmetic : the sign bit is replicated (right shift)4. Complete Arithmetic Logic Shift Unit
Combine the three sections behind one output MUX:
Select lines S3 S2 S1 S0 and the input carry Cin:
S3 S2 | Section chosen
------+---------------
0 0 | Arithmetic (S1 S0 and Cin choose which of the 8)
0 1 | Logic (S1 S0 choose AND/OR/XOR/NOT)
1 0 | Shift right
1 1 | Shift leftThe standard 14-operation ALU table
| S3 | S2 | S1 | S0 | Cin | Operation | Function |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | F = A | Transfer A |
| 0 | 0 | 0 | 0 | 1 | F = A + 1 | Increment A |
| 0 | 0 | 0 | 1 | 0 | F = A + B | Addition |
| 0 | 0 | 0 | 1 | 1 | F = A + B + 1 | Add with carry |
| 0 | 0 | 1 | 0 | 0 | F = A + B' | Subtract with borrow |
| 0 | 0 | 1 | 0 | 1 | F = A + B' + 1 | Subtraction |
| 0 | 0 | 1 | 1 | 0 | F = A − 1 | Decrement A |
| 0 | 0 | 1 | 1 | 1 | F = A | Transfer A |
| 0 | 1 | 0 | 0 | X | F = A ∧ B | AND |
| 0 | 1 | 0 | 1 | X | F = A ∨ B | OR |
| 0 | 1 | 1 | 0 | X | F = A ⊕ B | XOR |
| 0 | 1 | 1 | 1 | X | F = A' | Complement A |
| 1 | 0 | X | X | X | F = shr A | Shift right A |
| 1 | 1 | X | X | X | F = shl A | Shift left A |
5. Status Flags
Every ALU produces condition flags examined by conditional branch instructions:
| Flag | Set when |
|---|---|
| C (Carry) | A carry out of the MSB occurred |
| S (Sign) | The MSB of the result is 1 (negative) |
| Z (Zero) | The whole result is 0 |
| V (Overflow) | C(n) ⊕ C(n−1) = 1 — signed overflow |
| P (Parity) | The result has even (or odd) parity |
Z is generated by a NOR gate over ALL result bits:
Z = (F7 + F6 + ... + F0)'6. Worked Micro-operation Traces
Let A = 1011 (11), B = 0110 (6), 4-bit registers.
ADD : F = A + B = 1011 + 0110 = 1 0001 -> F = 0001, C = 1
SUBTRACT : F = A + B' + 1 = 1011 + 1001 + 1 = 1 0101 -> F = 0101 (5), C=1 discard
Check: 11 - 6 = 5 ✓
INCREMENT A : 1011 + 1 = 1100 (12) ✓
DECREMENT A : 1011 + 1111 = 1 1010 -> 1010 (10) ✓
AND : 1011 ^ 0110 = 0010
OR : 1011 v 0110 = 1111
XOR : 1011 ⊕ 0110 = 1101
COMPLEMENT A : 0100
SHR A : 0101 (logical)
SHL A : 0110 (logical, MSB lost)
CIR A : 1101 (LSB 1 wraps to MSB)
CIL A : 0111 (MSB 1 wraps to LSB)
ASHR A : 1101 (sign bit 1 replicated)7. Hardware Cost Summary
| Section | Per bit | For n bits |
|---|---|---|
| Arithmetic | 1 full adder + 1 4:1 MUX | n adders, n MUXes |
| Logic | 4 gates + 1 4:1 MUX | 4n gates, n MUXes |
| Shift | 1 4:1 MUX | n MUXes |
| Output select | 1 4:1 MUX | n MUXes |
Total for a 16-bit ALU with 14 operations:
16 full adders + 64 logic gates + 64 multiplexers, approximately.
IC 74181 packs a 4-bit version of exactly this into one chip.The ALU can now perform every micro-operation. The remaining question of Unit III is: who tells it which one to perform, and when? That is the instruction cycle.