Decoder

A decoder converts an n-bit binary code into 2^n output lines, activating exactly one of them. It answers the question: "which one of the 2^n possibilities does this code name?"

1. 2-to-4 Decoder

   Y0 = E . A1' . A0'          Y2 = E . A1 . A0'
   Y1 = E . A1' . A0           Y3 = E . A1 . A0

   Each output IS a minterm.  This is the key fact.

2. 3-to-8 Decoder

   Y(i) = minterm(i) of A2 A1 A0, gated by E

   Y0 = A2'A1'A0'    Y4 = A2 A1'A0'
   Y1 = A2'A1'A0     Y5 = A2 A1'A0
   Y2 = A2'A1 A0'    Y6 = A2 A1 A0'
   Y3 = A2'A1 A0     Y7 = A2 A1 A0

   Hardware: 3 inverters + 8 three-input AND gates

3. Active-High vs Active-Low Outputs

Most TTL decoders (74138, 74154) are active-low because NAND is the cheaper gate. In an active-low decoder each output is a maxterm complement: Y(i)' = m(i).

4. Enable Input and Cascading

   Build a 4-to-16 decoder from two 3-to-8 decoders:

      A2 A1 A0  -> both decoders' code inputs
      A3        -> Enable of decoder-1 through an INVERTER (active when A3 = 0)
                -> Enable of decoder-2 directly       (active when A3 = 1)

      A3 = 0  ->  decoder 1 gives Y0..Y7
      A3 = 1  ->  decoder 2 gives Y8..Y15

   Build a 5-to-32 decoder:  four 3-to-8 decoders + one 2-to-4 decoder
                             (the 2:4 decodes A4 A3 and drives the four enables)

5. Decoder as a Universal Function Generator

Because every output is a minterm, a decoder plus one OR gate implements any function, and several functions can share one decoder — this is its big advantage over the MUX.

   Implement a FULL ADDER with one 3-to-8 decoder and two OR gates.

   S    = Σm(1, 2, 4, 7)   ->  S    = Y1 + Y2 + Y4 + Y7
   Cout = Σm(3, 5, 6, 7)   ->  Cout = Y3 + Y5 + Y6 + Y7

   Inputs A, B, Cin -> decoder inputs A2 A1 A0.
   One decoder serves BOTH outputs.

Rule of thumb: if the function has more than half its minterms as 1s, OR the complement outputs and invert — fewer OR-gate inputs.

6. Memory Address Decoding — the real CPU application

This is why decoders exist in every computer.

   A CPU has a 16-bit address bus (A15..A0) -> 64K addressable locations.
   Memory is built from 4K x 8 chips, each needing 12 address lines (A11..A0).

   A11..A0  -> the address pins of every chip (selects the word inside a chip)
   A15..A12 -> a 4-to-16 DECODER -> one output enables exactly ONE chip (CS)

   Address map:
      Chip 0: 0000H - 0FFFH        Chip 4: 4000H - 4FFFH
      Chip 1: 1000H - 1FFFH        ...
      Chip 2: 2000H - 2FFFH        Chip F: F000H - FFFFH
      Chip 3: 3000H - 3FFFH

Numerical you may be asked:

   Q: How many 2K x 8 chips are needed for 16K x 8 memory, and how is
      the decoder arranged?

   Number of chips  = 16K / 2K = 8 chips
   Address lines per chip = log2(2K) = 11  (A10..A0)
   Chip select lines = log2(8) = 3         (A13..A11)
   Decoder needed   = 3-to-8 decoder
   Total address lines = 14  (16K = 2^14)

7. Other Applications

8. Encoder vs Decoder Preview

Summary

   n inputs -> 2^n outputs;  output(i) = minterm(i)
   Decoder + OR gates  = any set of functions sharing one decoder
   Decoder + enable    = de-multiplexer
   Decoder + address   = chip select in a memory system

Next lesson: the encoder, and the priority logic that fixes its one serious flaw.