Why General Registers?
The basic computer of the previous lessons has one accumulator. Every operation must pass through AC and therefore through memory, which is slow.
Memory access time ~ 50-100 ns (main memory)
Register access time ~ 1 ns
A CPU with 8-32 general-purpose registers can keep intermediate
results on-chip, dramatically reducing memory traffic.
General register organization = a set of registers plus a common ALU, interconnected by buses, with the source, destination and operation all selected by fields of a control word.
1. The Register File Architecture
Components:
- 7 registers R1..R7 (plus an external input)
- Two 8-to-1 MUXes forming bus A and bus B (the two ALU operands)
- An ALU performing the selected micro-operation
- A 3-to-8 decoder selecting the destination register
- Everything is controlled by ONE control word.
2. The Control Word
3 3 3 5
+------+------+------+--------+
| SELA | SELB | SELD | OPR | = 14 bits
+------+------+------+--------+
SELA : selects the source for bus A (the first operand)
SELB : selects the source for bus B (the second operand)
SELD : selects the destination register
OPR : selects the ALU operation
Encoding of SELA / SELB
| Binary | SELA source | SELB source |
|---|
| 000 | Input | Input |
| 001 | R1 | R1 |
| 010 | R2 | R2 |
| 011 | R3 | R3 |
| 100 | R4 | R4 |
| 101 | R5 | R5 |
| 110 | R6 | R6 |
| 111 | R7 | R7 |
Encoding of SELD
| Binary | Destination |
|---|
| 000 | None (result discarded — used for compare) |
| 001 | R1 |
| 010 | R2 |
| … | … |
| 111 | R7 |
Encoding of OPR (the ALU operation)
| OPR | Operation | Symbol |
|---|
| 00000 | Transfer A | TSFA |
| 00001 | Increment A | INCA |
| 00010 | Add A + B | ADD |
| 00101 | Subtract A − B | SUB |
| 00110 | Decrement A | DECA |
| 01000 | AND A and B | AND |
| 01010 | OR A and B | OR |
| 01100 | XOR A and B | XOR |
| 01110 | Complement A | COMA |
| 10000 | Shift right A | SHRA |
| 11000 | Shift left A | SHLA |
3. Worked Micro-operation Encodings
Micro-operation: R1 <- R2 - R3
SELA = R2 = 010
SELB = R3 = 011
SELD = R1 = 001
OPR = SUB = 00101
Control word: 010 011 001 00101
Micro-operation: R4 <- R4 v R5 (OR)
SELA = 100, SELB = 101, SELD = 100, OPR = 01010
Control word: 100 101 100 01010
Micro-operation: R7 <- R1 (transfer)
SELA = 001, SELB = 000 (don't care), SELD = 111, OPR = 00000
Control word: 001 000 111 00000
Micro-operation: Output <- R2 (send R2 to the external output)
SELA = 010, SELB = xxx, SELD = 000 (none), OPR = 00000
Control word: 010 000 000 00000
Micro-operation: R4 <- shl R4
SELA = 100, SELB = 000, SELD = 100, OPR = 11000
Control word: 100 000 100 11000
Micro-operation: R5 <- 0 (clear)
Clear is XOR with itself:
SELA = 101, SELB = 101, SELD = 101, OPR = 01100 (XOR)
Control word: 101 101 101 01100
4. Complete Worked Table
| Micro-operation | SELA | SELB | SELD | OPR | Control word |
|---|
| R1 ← R2 − R3 | R2 | R3 | R1 | SUB | 010 011 001 00101 |
| R4 ← R4 ∨ R5 | R4 | R5 | R4 | OR | 100 101 100 01010 |
| R6 ← R6 + 1 | R6 | — | R6 | INCA | 110 000 110 00001 |
| R7 ← R1 | R1 | — | R7 | TSFA | 001 000 111 00000 |
| Output ← R2 | R2 | — | None | TSFA | 010 000 000 00000 |
| Output ← Input | Input | — | None | TSFA | 000 000 000 00000 |
| R4 ← shl R4 | R4 | — | R4 | SHLA | 100 000 100 11000 |
| R5 ← 0 | R5 | R5 | R5 | XOR | 101 101 101 01100 |
5. Advantages of General Register Organization
| Advantage | Why |
|---|
| Fewer memory references | Intermediates stay in registers |
| Faster execution | Register access is ~50× faster than memory |
| Shorter instructions | A 3-bit register field vs a 16-bit address |
| Flexible operand selection | Any register can be any operand |
| Compiler friendly | Register allocation is a well-solved optimisation |
| Supports 2- and 3-address formats | R1 ← R2 + R3 in one instruction |
6. Accumulator vs General Register vs Stack Organization
| Basis | Accumulator (single-AC) | General register | Stack |
|---|
| Operand location | One in AC, one in memory | Registers (and memory) | Top of stack |
| Instruction format | 1-address | 2- or 3-address | 0-address |
| Example: X = A + B | LOAD A; ADD B; STORE X | MOV R1,A; ADD R1,B; MOV X,R1 | PUSH A; PUSH B; ADD; POP X |
| Instruction length | Short | Medium | Very short |
| Program length | Long | Short | Medium |
| Memory traffic | High | Low | Medium |
| Hardware | Simple | Moderate | Simple |
| Examples | Basic computer, 8085 (partly) | x86, ARM, MIPS, RISC-V | Java VM, older Burroughs machines |
7. Register Windows (bonus — RISC concept)
Problem: every procedure call must save and restore registers -> slow.
Solution (SPARC): the register file is much larger than what is
visible at once. A moving WINDOW exposes a subset:
+-------------------+
| Incoming params | <- overlaps the caller's outgoing block
+-------------------+
| Local variables |
+-------------------+
| Outgoing params | <- overlaps the callee's incoming block
+-------------------+
A call simply moves the window; the overlap passes the parameters
with ZERO register copying.
Summary
Control word = SELA | SELB | SELD | OPR
SELA, SELB : 8-to-1 MUX select for the two ALU operand buses
SELD : 3-to-8 decoder select for the destination
OPR : ALU function select
Encoding a micro-operation = filling in these four fields.
The next lesson covers the alternative organization named in that comparison table: the stack.
