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Unit 2 — Combinational Circuits: Design Procedure

Lesson 15 of 49 in the free Computer Organization and Architecture notes on Siksha Sarovar, written by Rohit Jangra.

Combinational vs Sequential Circuits

Unit II covers both families. Knowing the difference is the first question of almost every paper.

BasisCombinationalSequential
Output depends onPresent inputs onlyPresent inputs and past state
MemoryNonePresent (flip-flops / latches)
ClockNot requiredUsually required
FeedbackNonePresent
Design toolTruth table, K-mapState table, state diagram, excitation table
ExamplesAdder, MUX, decoder, encoder, comparatorFlip-flop, register, counter, RAM

The Standard Design Procedure

   1. Understand the problem; count inputs and outputs.
   2. Assign symbols to input and output variables.
   3. Build the TRUTH TABLE relating them (mark don't cares).
   4. Derive a simplified expression for EACH output (K-map).
   5. Draw the logic diagram.
   6. Verify against the truth table.

Worked Design 1 — Binary to Gray Code Converter (4-bit)

   Inputs : B3 B2 B1 B0      Outputs: G3 G2 G1 G0

   From the Gray-code rule:
       G3 = B3
       G2 = B3 ⊕ B2
       G1 = B2 ⊕ B1
       G0 = B1 ⊕ B0

   Hardware: 3 XOR gates. (K-maps would produce the same checkerboards.)
B3 B2 B1 B0G3 G2 G1 G0
0 0 0 00 0 0 0
0 0 0 10 0 0 1
0 0 1 00 0 1 1
0 0 1 10 0 1 0
0 1 0 00 1 1 0
1 0 0 01 1 0 0
1 1 1 11 0 0 0

Worked Design 2 — Odd Parity Generator (3 data bits)

   The parity bit P must make the TOTAL number of 1s odd.

   P = (D2 ⊕ D1 ⊕ D0)'      for ODD parity
   P =  D2 ⊕ D1 ⊕ D0        for EVEN parity

   Check D2D1D0 = 011 (two 1s):
      even-parity P = 0 ⊕ 1 ⊕ 1 = 0  -> total 1s = 2 (even) ✓
      odd-parity  P = (0)' = 1        -> total 1s = 3 (odd)  ✓

A parity checker is the same XOR tree applied to data + parity bit; a non-zero result means an error was detected (single-bit errors only).

Worked Design 3 — BCD to Excess-3 Converter

   Excess-3 = BCD + 3.  Inputs A B C D (BCD 0..9), outputs W X Y Z.
   Inputs 1010..1111 are DON'T CARES.

   W = A + BC + BD          = A + B(C + D)
   X = B'C + B'D + BC'D'    = B'(C + D) + BC'D'
   Y = CD + C'D'            = (C ⊕ D)'
   Z = D'

   Verify BCD 5 = 0101  ->  W = 0 + 1(0+1) = 1
                            X = 0 + 1.0.0 ... B=1 so X = B'(C+D) + BC'D' = 0 + 1.1.0 = 0
                            Y = (0 ⊕ 1)' = 0
                            Z = 1
                            WXYZ = 1000 = 8 = 5 + 3  ✓

Analysis Procedure (the reverse direction)

Given a circuit, find what it does:

   1. Label every gate output.
   2. Write the Boolean expression for each labelled output.
   3. Substitute back until the final outputs are in terms of inputs only.
   4. Build the truth table.
   5. Name the function.

The Four Standard MSI Blocks of Unit II

BlockInputsSelect/ControlOutputsOne-line job
Multiplexer2^n datan select1Choose one of many
De-multiplexer1 datan select2^nRoute to one of many
Decodern(enable)2^nActivate exactly one output line
Encoder2^n(enable)nReport which line is active

The next four lessons take these one at a time.