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Registers, Counters, Latches and The Master-Slave Flip-Flop — Computer Organization and Architecture Notes

4-Bit Serial-In Serial-Out (SISO) Shift Register

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SR Latch (NAND-Based)

S (active-low)	R (active-low)	Q	Q'
0	1	1	0	(Set)
1	0	0	1	(Reset)
1	1	Q	Q'	(Hold)
0	0	1	1	Forbidden

The NAND-based SR latch uses active-LOW inputs (inputs are inverted). Forbidden state: both S and R = 0 (both outputs = 1 simultaneously).

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Register Types

Type	Full Name	Description	Use Case
SISO	Serial-In, Serial-Out	1-bit in/out per clock; data shifts through	Serial communication, delay lines
SIPO	Serial-In, Parallel-Out	1-bit in per clock; all bits out simultaneously	Serial-to-parallel conversion
PISO	Parallel-In, Serial-Out	All bits loaded; 1-bit out per clock	Parallel-to-serial conversion
PIPO	Parallel-In, Parallel-Out	All bits in/out simultaneously	CPU registers, buffer

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Shift Register Arithmetic Property

Left shift by 1 = multiply by 2 (shift contents left, fill LSB with 0)
Right shift by 1 = divide by 2 (shift contents right, fill MSB with 0 for unsigned)
Example: 0101 (5) left-shift → 1010 (10) ✓
Example: 1010 (10) right-shift → 0101 (5) ✓

This is exploited by compilers for fast multiply/divide by powers of 2.

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2-Bit Ripple Counter State Diagram

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Ripple (Asynchronous) vs Synchronous Counter

Feature	Ripple (Asynchronous)	Synchronous
Clock	Only LSB FF clocked by system clock	All FFs clocked simultaneously
Speed	Slower — carry ripples through all FFs	Faster — no ripple delay
Glitches	Yes — intermediate invalid states during transition	No — all FFs change together
Hardware	Simple — each FF output drives next FF clock	Complex — requires combinational logic
Max frequency	Limited by cumulative delay	Higher frequency possible

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Modulo-N Counter Summary

Counter	Flip-Flops Needed	Count Sequence	Application
MOD-2	1	0,1,0,1,...	Divide-by-2, clock divider
MOD-4	2	0,1,2,3,0,...	2-bit counter
MOD-8	3	0–7, repeat	3-bit counter, octal
MOD-10 (BCD)	4 (with reset at 10)	0–9, repeat	Decimal counter, clock
MOD-16	4	0–15, repeat	Hex counter, 4-bit

For MOD-N: need ⌈log₂N⌉ flip-flops.

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Ring Counter vs Johnson Counter (4-bit)

Feature	Ring Counter	Johnson Counter (Twisted Ring)
Bit pattern	1000, 0100, 0010, 0001	0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001
States	N states for N flip-flops	2N states for N flip-flops
Decoding	Simple — no extra logic	Requires 2-input AND gates
Self-correcting	No	No
Application	Sequence generator, timing	Frequency divider, control sequence

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Master-Slave JK Flip-Flop

The master-slave configuration consists of:

Master FF: Positive-level triggered; samples J and K when CLK=1
Slave FF: Negative-level triggered; transfers master output to slave when CLK=0

This ensures the output changes only once per clock cycle on the falling edge, eliminating the race-around condition. Modern edge-triggered FFs (using transmission gates) provide the same result in fewer transistors.

📝 Exam Tips: - SISO: data enters and exits serially — useful for serial communications - n-bit ripple counter needs n T flip-flops; each successive FF toggles at half the frequency - Ring counter: exactly 1 bit is 1 at any time; Johnson counter: has 2N states - MOD-N counter: if N is not power of 2, use reset logic when count reaches N