Registers
A register is a group of n flip-flops sharing a common clock, storing an n-bit word. It is the fundamental storage unit inside a CPU — Unit III is built entirely on registers.
1. Simple 4-bit Register
Four D flip-flops, common clock, common clear.
On each clock edge: A3A2A1A0 <- I3I2I1I0
IC 74175 is exactly this: quad D flip-flop with common clock and clear.2. Register with Parallel Load
A plain register loads new data on every clock edge — usually undesirable. A load control fixes this.
Method 1 (WRONG in synchronous design): gate the clock.
CLK(FF) = CLK . LOAD
-> creates clock skew and glitches. Never do this.
Method 2 (CORRECT): feed the output back through a MUX.
D(i) = LOAD . I(i) + LOAD' . Q(i)
LOAD = 1 -> new data loaded
LOAD = 0 -> the flip-flop reloads its own value (holds)3. Shift Registers
A shift register moves its stored bits one position per clock, by connecting each flip-flop's output to the next one's input.
Q0 -> Q1 -> Q2 -> Q3 (right shift)
D0 = Serial In
D1 = Q0
D2 = Q1
D3 = Q2
Serial Out = Q3The four types
| Type | Data in | Data out | Clocks needed to load / read |
|---|---|---|---|
| SISO Serial-In Serial-Out | 1 bit per clock | 1 bit per clock | n to load, n to read |
| SIPO Serial-In Parallel-Out | 1 bit per clock | all n at once | n to load, 1 to read |
| PISO Parallel-In Serial-Out | all n at once | 1 bit per clock | 1 to load, n to read |
| PIPO Parallel-In Parallel-Out | all n at once | all n at once | 1 to load, 1 to read |
SISO worked trace
Load 1011 serially (MSB first) into a 4-bit right-shift register.
Initial state Q3Q2Q1Q0 = 0000.
Clock | Serial In | Q0 Q1 Q2 Q3
------+-----------+------------
0 | - | 0 0 0 0
1 | 1 | 1 0 0 0
2 | 0 | 0 1 0 0
3 | 1 | 1 0 1 0
4 | 1 | 1 1 0 1
After 4 clocks the word is fully loaded. After 4 MORE clocks it emerges
at the serial output, one bit per clock.4. Universal Shift Register
A universal (bidirectional) shift register performs four operations selected by two control bits:
| S1 | S0 | Operation |
|---|---|---|
| 0 | 0 | Hold (no change) |
| 0 | 1 | Shift right |
| 1 | 0 | Shift left |
| 1 | 1 | Parallel load |
Each stage uses a 4-to-1 MUX:
I0 of the MUX = Q(i) (hold)
I1 of the MUX = Q(i+1) (shift right)
I2 of the MUX = Q(i-1) (shift left)
I3 of the MUX = parallel input I(i)
D(i) = MUX output, selects = S1 S0
IC 74194 is a 4-bit universal shift register built exactly this way.5. Shift Register Applications
| Application | How it works |
|---|---|
| Serial ↔ parallel conversion | SIPO in a UART receiver, PISO in a transmitter |
| Multiplication / division by 2 | Left shift = ×2, right shift = ÷2 (arithmetic shift preserves the sign bit) |
| Delay line | An n-stage SISO delays a serial stream by n clocks |
| Sequence generator | Feedback from Q outputs produces a repeating pattern |
| Ring counter / Johnson counter | Feedback variants (next lesson) |
| LFSR (pseudo-random generator) | XOR feedback of selected taps; used in CRC and scramblers |
| Data transfer between registers | Serial transfer needs only one wire instead of n |
Arithmetic vs logical shift
Logical right shift of 1011: 0101 (0 shifted in)
Arithmetic right shift of 1011: 1101 (sign bit replicated)
For signed numbers, ONLY the arithmetic shift preserves the value:
1011 = -5 (2's complement); -5 / 2 = -2.5 -> -3 = 1101 ✓
Logical shift would give 0101 = +5, which is wrong.6. Latch vs Register vs Shift Register
| Latch | Register | Shift register | |
|---|---|---|---|
| Bits stored | 1 | n | n |
| Clock | Level (enable) | Edge | Edge |
| Data movement | None | None | One position per clock |
| Typical use | Bus holding, temporary storage | CPU registers, buffers | Serial I/O, delays, counters |
7. Serial vs Parallel Transfer Between Registers
PARALLEL transfer: n wires, 1 clock, fast, expensive in wiring.
R2 <- R1 happens in a single clock pulse.
SERIAL transfer: 1 wire, n clocks, slow, cheap.
Shift out of R1 and into R2 simultaneously, n times.
Control: a shift-control signal ANDed with the clock enables
exactly n pulses.This distinction reappears in Unit III (bus transfer) and Unit IV (serial asynchronous communication).
Summary
Register = n flip-flops + common clock
Parallel load = MUX feedback (never gate the clock)
Shift register = each Q feeds the next D
SISO SIPO PISO PIPO = the four data-movement combinations
Universal SR = 4:1 MUX per stage -> hold, shift L, shift R, loadThe last Unit II lesson turns these same flip-flops into counters.