Counters

A counter is a sequential circuit that steps through a fixed sequence of states on successive clock pulses. It is the second great application of flip-flops (after registers).

1. Asynchronous (Ripple) Counter

Only the first flip-flop receives the external clock; each subsequent flip-flop is clocked by the previous stage's output.

   3-bit ripple UP counter (negative-edge-triggered T flip-flops, T = 1):

      CLK -> FF0 (Q0) -> clocks FF1 (Q1) -> clocks FF2 (Q2)

   Count | Q2 Q1 Q0
   ------+---------
     0   | 0  0  0
     1   | 0  0  1
     2   | 0  1  0
     3   | 0  1  1
     4   | 1  0  0
     5   | 1  0  1
     6   | 1  1  0
     7   | 1  1  1
     8   | 0  0  0   (rolls over)

   UP counter   : connect the next stage's clock to Q  (for negative-edge FFs)
                  or to Q' (for positive-edge FFs)
   DOWN counter : the opposite connection

The ripple problem

   Each flip-flop must wait for the previous one to settle.

   Total settling delay = n . t(pd)

   3-bit counter, t(pd) = 10 ns  ->  30 ns before the count is valid.
   During those 30 ns the outputs show TRANSIENT WRONG VALUES (glitches).

   Example: 0111 -> 1000 passes through 0110, 0100, 0000 momentarily.
   Any circuit decoding the count can see these spikes -> DECODING GLITCHES.

   Maximum frequency:  f(max) = 1 / (n . t(pd))

2. Synchronous Counter

All flip-flops receive the same clock simultaneously; combinational logic decides which ones toggle.

   3-bit synchronous UP counter with T flip-flops:

      T0 = 1
      T1 = Q0
      T2 = Q0 . Q1
      T3 = Q0 . Q1 . Q2         (for a 4-bit version)

   Rule: a bit toggles when ALL lower bits are 1.

   Settling delay = t(pd) + t(AND)   -> INDEPENDENT of n
   f(max) is much higher, and there are no decoding glitches.

3. Asynchronous vs Synchronous

4. Mod-N Counter (the standard numerical)

A mod-N counter has N distinct states (0 to N−1).

   Number of flip-flops required:  n = ceil( log2(N) )

   Mod-8  -> 3 FFs (exactly)
   Mod-10 -> 4 FFs (16 possible states, 6 unused)
   Mod-6  -> 3 FFs (8 possible states, 2 unused)
   Mod-12 -> 4 FFs

Building a mod-N ripple counter — the reset method

   Design a MOD-6 counter (counts 000..101, then resets).

   1. n = ceil(log2 6) = 3 flip-flops.
   2. The counter must RESET when it reaches 6 = 110.
   3. Feed Q2 and Q1 into a NAND gate; its output drives the
      active-low CLEAR of all three flip-flops.

      CLEAR = (Q2 . Q1)'

   4. The instant the count hits 110, CLEAR goes low and forces 000.

   Sequence: 000, 001, 010, 011, 100, 101, (110 for a few ns), 000, ...

The glitch caveat: state 110 does exist for a few nanoseconds. This "spike" is why the reset method is considered a quick hack; a properly designed synchronous mod-6 counter never enters state 110 at all.

Design a synchronous MOD-5 counter with JK flip-flops

   States: 000 -> 001 -> 010 -> 011 -> 100 -> 000

   Present  | Next    | J2 K2 | J1 K1 | J0 K0
   Q2 Q1 Q0 | Q2 Q1 Q0|       |       |
   ---------+---------+-------+-------+-------
   0  0  0  | 0  0  1 | 0  X  | 0  X  | 1  X
   0  0  1  | 0  1  0 | 0  X  | 1  X  | X  1
   0  1  0  | 0  1  1 | 0  X  | X  0  | 1  X
   0  1  1  | 1  0  0 | 1  X  | X  1  | X  1
   1  0  0  | 0  0  0 | X  1  | 0  X  | 0  X
   1  0  1  |    unused (don't care)
   1  1  0  |    unused
   1  1  1  |    unused

   K-maps (using the unused states as don't cares) give:

      J0 = Q2'        K0 = 1
      J1 = Q0         K1 = Q0
      J2 = Q1.Q0      K2 = 1

5. BCD / Decade Counter (Mod-10)

   Counts 0000 to 1001, then resets to 0000.

   Ripple version:  CLEAR = (Q3 . Q1)'      (detects 1010 = 10)
   Synchronous version: full design with 6 don't-care states.

   IC 7490 = decade counter,  IC 7493 = 4-bit binary counter.

6. Ring Counter

A shift register whose serial output is fed back to its serial input.

   4-bit ring counter, initialised to 1000:

   Clock | Q3 Q2 Q1 Q0
   ------+------------
     0   | 1  0  0  0
     1   | 0  1  0  0
     2   | 0  0  1  0
     3   | 0  0  0  1
     4   | 1  0  0  0   (repeats)

   Number of states = n (one per flip-flop)
   Only ONE flip-flop is 1 at a time -> ONE-HOT encoding
   NO decoding logic needed — each output IS a state signal.

7. Johnson (Twisted-Ring / Switch-Tail) Counter

Same as a ring counter, but the complement Q' of the last stage feeds back.

   4-bit Johnson counter starting at 0000:

   Clock | Q3 Q2 Q1 Q0
   ------+------------
     0   | 0  0  0  0
     1   | 1  0  0  0
     2   | 1  1  0  0
     3   | 1  1  1  0
     4   | 1  1  1  1
     5   | 0  1  1  1
     6   | 0  0  1  1
     7   | 0  0  0  1
     8   | 0  0  0  0   (repeats)

   Number of states = 2n  ->  twice as many as a ring counter
   Decoding needs only 2-input AND gates (each state has a unique
   adjacent 0-1 or 1-0 boundary).

8. Counter Comparison Table

   For 8 states:
      Binary  -> 3 flip-flops + decoding logic
      Johnson -> 4 flip-flops + simple 2-input decoding
      Ring    -> 8 flip-flops + no decoding

9. Up-Down Counter

   A mode line M selects the direction:

      T(i) for UP   = product of all lower Q
      T(i) for DOWN = product of all lower Q'

      T1 = M.Q0 + M'.Q0'
      T2 = M.Q1.Q0 + M'.Q1'.Q0'
      ...

   IC 74193 is a 4-bit synchronous up/down counter with parallel load.

10. Applications of Counters

Forward reference: the T0–T3 sequence counter that times the instruction cycle in Unit III is nothing more than a 2-bit counter feeding a 2-to-4 decoder. Everything from Unit II reappears in the CPU.

Summary

   Ripple counter    : simple, slow, glitchy;  delay = n.t(pd)
   Synchronous       : one clock, extra AND logic;  delay = t(pd)
   Mod-N             : n = ceil(log2 N);  reset at N (async) or design the
                       state table properly (sync)
   Ring counter      : n states, one-hot, zero decoding
   Johnson counter   : 2n states, simple decoding

Unit II is complete. Unit III now stops looking at individual flip-flops and starts treating whole registers as the basic unit — the language of register transfer.