The Interconnection Problem

   With n registers of w bits each, connecting EVERY register to EVERY
   other register directly requires:

      n x (n - 1) sets of w wires

   For 8 registers of 16 bits:  8 x 7 x 16 = 896 wires.  Unmanageable.

   Solution: a COMMON BUS — one shared set of w lines that any register
   can drive and any register can read.

1. Common Bus System

A bus is a set of common lines, one per bit, through which binary information is transferred one word at a time between registers.

   Two control decisions per transfer:
      1. WHICH register drives the bus  -> the SELECT lines (a MUX)
      2. WHICH register loads from the bus -> the LOAD signals

2. Bus Built from Multiplexers

   For 4 registers of 4 bits each:

      Bus line 0  <- 4-to-1 MUX with inputs R0(0), R1(0), R2(0), R3(0)
      Bus line 1  <- 4-to-1 MUX with inputs R0(1), R1(1), R2(1), R3(1)
      Bus line 2  <- 4-to-1 MUX with inputs R0(2), R1(2), R2(2), R3(2)
      Bus line 3  <- 4-to-1 MUX with inputs R0(3), R1(3), R2(3), R3(3)

   All four MUXes share the SAME select lines S1 S0.

   Number of MUXes needed  = number of BITS per register (w)
   Size of each MUX        = number of REGISTERS (n) to 1
   Select lines            = ceil(log2 n)

Standard numerical:

   Q: Construct a common bus for eight registers of 16 bits each
      using multiplexers.

   MUX size   = 8-to-1
   Number of MUXes = 16   (one per bit)
   Select lines    = 3    (log2 8)
   Total inputs to each MUX = 8

3. Bus Built from Three-State Buffers

A cheaper alternative: give every register's output a tri-state buffer and let a decoder enable exactly one.

   A three-state (tri-state) buffer has three output conditions:

      Control = 1  ->  output = input   (logic 0 or logic 1)
      Control = 0  ->  HIGH IMPEDANCE (Hi-Z) — electrically disconnected

   Because a disabled buffer is effectively removed from the circuit,
   MANY buffers can share one wire, provided only ONE is enabled at a time.

   For 4 registers of 4 bits:
      4 tri-state buffers per bus line  x 4 lines = 16 buffers
      1 (2-to-4) decoder drives the enables

   If TWO buffers are enabled simultaneously -> BUS CONTENTION
   (a direct short between a 0-driver and a 1-driver) -> can destroy the chip.

4. Register Transfer via the Bus

   The RTL statement           R1 <- R2

   is implemented on a bus as:

      BUS <- R2,  R1 <- BUS

   which is usually abbreviated back to  R1 <- R2 , because the bus is
   understood. In a formal answer, write both steps.

5. Memory Transfer

Memory is treated as one enormous register file, addressed by the Address Register (AR) and communicating through the Data Register (DR).

   Notation:   M[AR]   = the memory word selected by the address in AR

   READ  :   DR <- M[AR]
   WRITE :   M[AR] <- DR       (some books write M <- DR)

Memory sizing arithmetic

   A memory of 2^k words x n bits needs:
      k address lines  (so AR is k bits wide)
      n data lines     (so DR is n bits wide)

   Examples:
      1K x 8   ->  10 address lines, 8 data lines
      4K x 16  ->  12 address lines, 16 data lines
      64K x 8  ->  16 address lines, 8 data lines
      1M x 32  ->  20 address lines, 32 data lines

6. The Bus in a Basic Computer

   The basic computer of the next lessons has SEVEN registers plus memory
   sharing one 16-bit common bus, selected by three lines S2 S1 S0:

   S2 S1 S0 | Register selected
   ---------+------------------
    0  0  0 | (nothing / x)
    0  0  1 | AR   Address Register     (12 bits)
    0  1  0 | PC   Program Counter      (12 bits)
    0  1  1 | DR   Data Register        (16 bits)
    1  0  0 | AC   Accumulator          (16 bits)
    1  0  1 | IR   Instruction Register (16 bits)
    1  1  0 | TR   Temporary Register   (16 bits)
    1  1  1 | Memory unit               (16 bits)

   Registers narrower than 16 bits place their contents in the low-order
   lines; the high-order bus lines receive 0s.

7. Three-Bus vs Single-Bus Organisation

   Why three buses are faster for  R3 <- R1 + R2 :

      Single bus: needs 3 steps (R1 -> temp, R2 -> ALU, result -> R3)
      Three bus : R1 on bus A, R2 on bus B, ALU output on bus C -> ONE step.

Summary

   Bus       = shared set of lines for register-to-register transfer
   MUX bus   : w MUXes of size n-to-1;  select lines = log2(n)
   Tri-state : n buffers per line + decoder; one enable at a time
   Memory    : DR <- M[AR]  (read),  M[AR] <- DR  (write)
   2^k x n memory  ->  k address lines, n data lines

Registers, buses and memory are now in place. The next lesson defines the instructions that tell them what to do.