Addressing Modes
An addressing mode specifies a rule for interpreting or modifying the address field of an instruction before the operand is actually referenced.
Two reasons addressing modes exist:
1. To give programming flexibility — pointers, loop counters,
indexing into arrays, program relocation.
2. To reduce the number of address bits in the instruction.Key term: the effective address (EA) is the address of the operand actually used, after the mode has been applied.
The Modes, One by One
1. Implied (Implicit) Mode
The operand is specified implicitly by the instruction itself.
Examples: CMA (complement the accumulator — AC is implied)
CLC (clear carry)
PUSH / POP (the stack pointer is implied)
No address field at all. Zero-address instructions are all implied mode.2. Immediate Mode
The OPERAND ITSELF is in the address field — no memory access.
MOV R1, #25 ; R1 <- 25 (the # marks an immediate)
EA: not applicable. Fastest mode. Used to initialise registers
and to supply constants.3. Register Mode
The operand is in a REGISTER named by the address field.
MOV R1, R2 ; R1 <- R2
EA: not a memory address — the register itself.
Very fast; the address field is small (log2 of the register count).4. Register Indirect Mode
The register holds the ADDRESS of the operand.
MOV R1, (R2) ; R1 <- M[R2]
EA = contents of R2
Advantage: the address field is small, yet a full-length address
can be reached. This is how POINTERS are implemented.5. Auto-increment / Auto-decrement Mode
Register indirect, with the register automatically adjusted.
MOV R1, (R2)+ ; R1 <- M[R2], then R2 <- R2 + 1
MOV R1, -(R2) ; R2 <- R2 - 1, then R1 <- M[R2]
Purpose-built for stepping through ARRAYS and for stack operations.6. Direct (Absolute) Mode
The address field IS the effective address.
LDA 500 ; AC <- M[500]
EA = 500
Simple, but the address field must be wide enough for the whole
address space, and the code cannot be relocated.7. Indirect Mode
The address field holds the address OF THE ADDRESS.
LDA (500) ; AC <- M[ M[500] ]
EA = M[500]
Costs one extra memory access, but supports pointers and
allows a short address field to reach anywhere in memory.8. Relative Address Mode
EA = address field + PC
Used by branch instructions. The address field holds a signed
OFFSET from the current instruction.
Advantage: the code is POSITION INDEPENDENT — it can be loaded
anywhere in memory and still work. The offset field can be small
because branches are usually nearby.9. Indexed Address Mode
EA = address field + XR (index register)
The address field holds the BASE of an array; the index register
holds the element number. Incrementing XR walks the array.10. Base Register Mode
EA = address field + BR (base register)
Looks like indexed mode, but the roles are swapped:
Indexed : address field = base of the array, register = displacement
Base : register = base of the segment, address field = displacement
Base mode is used for RELOCATION — the loader sets BR once and every
address in the program is automatically adjusted.The Standard Numerical
This exact problem, with these exact numbers, appears in paper after paper.
A two-word instruction is stored at addresses 200 and 201.
The address field of the instruction (at 201) contains 500.
PC = 200
R1 = 400 (a processor register)
XR = 100 (index register)
Memory contents:
M[200] = "Load to AC" (the instruction, mode field included)
M[201] = 500
M[399] = 450
M[400] = 700
M[500] = 800
M[600] = 900
M[702] = 325
M[800] = 300
PC is incremented to 202 during the fetch.| Addressing mode | Effective address | Content loaded into AC |
|---|---|---|
| Direct | 500 | 800 |
| Immediate | 201 | 500 |
| Indirect | 800 | 300 |
| Relative | 702 (= 202 + 500) | 325 |
| Indexed | 600 (= 500 + 100) | 900 |
| Register | — | 400 |
| Register indirect | 400 | 700 |
| Auto-increment | 400 | 700 (then R1 = 401) |
| Auto-decrement | 399 | 450 (R1 = 399 first) |
Working:
DIRECT : EA = 500 -> AC = M[500] = 800
IMMEDIATE : the operand is the second word itself,
so EA = 201 -> AC = 500
INDIRECT : EA = M[500] = 800 -> AC = M[800] = 300
RELATIVE : EA = PC + 500 = 202 + 500 = 702 -> AC = M[702] = 325
(PC is ALREADY incremented to 202 — the classic trap)
INDEXED : EA = XR + 500 = 100 + 500 = 600 -> AC = M[600] = 900
REGISTER : the operand is R1 itself -> AC = 400
REGISTER INDIRECT: EA = R1 = 400 -> AC = M[400] = 700
AUTO-INCREMENT : same as register indirect, then R1 becomes 401
-> AC = 700
AUTO-DECREMENT : R1 is decremented FIRST: 400 - 1 = 399
-> EA = 399 -> AC = M[399] = 450Complete Summary Table
| Mode | Effective address | Memory accesses for the operand | Main use |
|---|---|---|---|
| Implied | — | 0 | Stack ops, accumulator ops |
| Immediate | — (operand in the instruction) | 0 | Constants |
| Register | — (operand in a register) | 0 | Fast temporaries |
| Register indirect | EA = (R) | 1 | Pointers |
| Auto-increment | EA = (R), then R++ | 1 | Array traversal, stack pop |
| Auto-decrement | R−−, then EA = (R) | 1 | Reverse traversal, stack push |
| Direct | EA = A | 1 | Simple global variables |
| Indirect | EA = M[A] | 2 | Pointers, long addresses |
| Relative | EA = A + PC | 1 | Branches, position-independent code |
| Indexed | EA = A + XR | 1 | Arrays |
| Base register | EA = A + BR | 1 | Relocation, segmentation |
Choosing a Mode — the trade-off
Fewer memory accesses -> faster
More flexibility -> more accesses
Immediate / Register : 0 extra accesses, no flexibility
Direct : 1 access, no flexibility
Indirect : 2 accesses, full pointer flexibility
Indexed / Relative : 1 access + one addition, array/branch friendlyWorked Programming Examples
Sum an array of 100 elements starting at address 1000:
MOV XR, #0 ; immediate — index = 0
MOV AC, #0 ; immediate — sum = 0
LOOP:
ADD AC, 1000(XR) ; INDEXED — AC <- AC + M[1000 + XR]
INC XR ; implied
CMP XR, #100 ; immediate
BNE LOOP ; RELATIVE — PC <- PC + offset Follow a linked list:
LOOP:
MOV AC, (R1) ; REGISTER INDIRECT — read the node's data
MOV R1, 4(R1) ; INDEXED — R1 <- next pointer
BNZ LOOP ; RELATIVESummary
Effective address (EA) = the address of the operand after
the mode has been applied.
Remember the relative-mode trap: PC has ALREADY been incremented
past the instruction before the offset is added.Unit III is complete: instructions are defined, formatted, addressed and executed. Unit IV takes the finished CPU and connects it to the outside world and to the memory hierarchy.