16.1 The successive approximation (SAR) ADC

The SAR ADC is the workhorse of microcontroller-integrated ADCs. It converts in exactly N clock cycles for an N-bit output, using only one comparator — far less hardware than a flash ADC for the same resolution.

Block diagram

Conversion algorithm flowchart

Worked example — 4-bit SAR converting V_in = 11/16 of FSR

Each row shows the SAR register before the comparison, the resulting decision, and the register after.

Final code = 1011 = 11/16 of FSR. N = 4 cycles, exactly.

Strengths and weaknesses

Most microcontroller ADCs (AVR, STM32, PIC, ESP32, …) are SAR.

16.2 The counting (ramp) ADC

Algorithm

1. Reset the counter to 0.
2. Tick the clock. The counter increments → DAC output ramps up linearly.
3. When the DAC output crosses V_in, the comparator flips → stop the counter.
4. The counter value is the digital output.

Performance

• Conversion time depends on V_in: a near-FSR input takes 2^N clocks; a small input completes quickly.
• Worst-case latency for N = 10 bits at 1 MHz clock = 1024 µs ≈ 1 ms — very slow compared to SAR.
• Hardware is trivial — one counter + one DAC + one comparator.

Variants

• Tracking ADC. Replace the binary counter with an up/down counter that increments when V_in > V_dac and decrements when V_in < V_dac. Once locked, the counter "tracks" V_in continuously — useful for slowly varying signals.
• Servo ADC. Same idea but with hysteresis to prevent dithering on a noisy input.

16.3 SAR vs Counting at a glance

16.4 Worked example — pick the right ADC

Requirement: digitise an audio signal at 16 b resolution, 48 kSPS.

• Flash: 2^16 − 1 = 65 535 comparators. Impossible.
• Counting: at 16 b, worst case 65 536 clocks per sample × 48 000 samples / s = 3.15 GHz clock. Impossible.
• SAR: 16 clocks per sample × 48 000 = 770 kHz clock. Easily achievable, so this is the right architecture.

Real audio ADCs go even further and use sigma-delta converters (oversample at MHz rates and shape the noise into a high-frequency band before filtering).