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Unit 4: Quantization, Encoding & Flash (Parallel Comparator) ADC

Lesson 16 of 20 in the free Digital Electronics-II notes on Siksha Sarovar, written by Rohit Jangra.

15.1 Why we need ADCs

Almost every quantity we want to measure — temperature, voltage, pressure, microphone audio — is analog. The world is continuous. But the CPU we want to feed those signals into is digital — it understands only finite-precision numbers. An A/D Converter (ADC) is the bridge: it takes a continuous voltage at its input and produces an integer at its output.

Two operations happen inside every ADC, often interleaved:

  1. Sampling — taking snapshots of the analog input at fixed time intervals.
  2. Quantization & encoding — mapping each snapshot's voltage to one of 2^N discrete codes and outputting the binary code.

15.2 Quantization

Divide the input range [V_min, V_max] into 2^N equal steps, each of width

   Q = (V_max − V_min) / 2^N

Q is called the quantum or LSB voltage. Any sample that falls inside step k gets the code k.

Quantization error

   ε_q ∈ [−Q/2, +Q/2]

That is the best-case error of any ADC. You cannot do better than ±½ LSB without using more bits.

Resolution table

N (bits)Codes (2^N)Resolution (5 V FSR)Typical use
825619.5 mVCheap MCU peripherals
1010244.88 mVMost micro ADCs
1240961.22 mVHigh-end MCUs
1665 53676 µVAudio, instrumentation
2416 777 2160.30 µVLab-grade DMM / weigh scales

15.3 Encoding — the output representation

EncodingUse
Straight binaryMost general-purpose ADCs (0 → 0000…, FSR → 1111…)
Offset binaryBipolar inputs (midpoint = 1000…0)
Two's complementBipolar inputs that feed directly into a CPU adder
Sign-magnitudeSome audio codecs
Gray codeSome ADC internals (avoids decoder glitches before retiming)

15.4 The four ADC architectures in this unit

ADCSpeedResolutionCostWhere you see it
Flash (parallel comparator)Highest (Gsps)Low (≤ 8 b)HighestOscilloscopes, radar, gigabit ethernet
Successive approximation (SAR)Medium (Msps)Medium (8–18 b)LowMicrocontroller peripherals, data acquisition
Counting / dual-slopeLow (Hz–kHz)High (12–24 b)Very lowMultimeters, voltage panel meters
Voltage-to-frequency / timeLowHighVery lowIsolation barriers, integrating front ends

15.5 The flash (parallel comparator) ADC

For N output bits, the flash ADC needs:

  • 2^N equal resistors forming a voltage divider.
  • 2^N − 1 comparators, each comparing V_in against one tap.
  • A priority encoder to turn the thermometer code into binary.

How it works in one clock cycle

  1. The ladder produces 2^N − 1 reference voltages (k+0.5)·Q for k = 0…2^N − 2.
  2. Every comparator simultaneously says "V_in > ref_k ?" → outputs 1 or 0.
  3. The resulting pattern is a thermometer code — all 1s below some threshold, all 0s above.
  4. The priority encoder reports the highest k that is still 1 → binary output.

Because everything happens in parallel, one clock cycle is enough.

Thermometer-to-binary mapping (3-bit example)

V_in zoneThermometer (C6..C0)Priority encoder output
0 ≤ V_in < Q0000000000
Q ≤ V_in < 2Q0000001001
2Q ≤ V_in < 3Q0000011010
3Q ≤ V_in < 4Q0000111011
4Q ≤ V_in < 5Q0001111100
5Q ≤ V_in < 6Q0011111101
6Q ≤ V_in < 7Q0111111110
7Q ≤ V_in1111111111

Strengths and weaknesses

ProsCons
Single-cycle conversion — fastest possible2^N − 1 comparators → area/power explode
Pipeline-friendlyComparator offset → DNL/INL errors
No internal clock for the conversion itselfHuge input capacitance (one comparator gate × 2^N)

This is why flash ADCs are pretty much always ≤ 8 bits.

15.6 Worked example — design a 3-bit flash ADC for 0–5 V

  • FSR = 5 V, N = 3 → 8 codes, Q = 5 V / 8 = 0.625 V.
  • Reference tap voltages: 0.3125 V, 0.9375 V, 1.5625 V, 2.1875 V, 2.8125 V, 3.4375 V, 4.0625 V.
  • Components: 8 equal resistors (e.g. 1 kΩ) between V_ref and GND, 7 comparators (LM339 dies), 8-to-3 priority encoder (74LS148).

The total propagation delay is just t_comparator + t_encoder — typically under 50 ns even with garden-variety comparators.