17.1 Why integrating ADCs exist
The flash, SAR and counting architectures all sample the input at a single instant. Their accuracy therefore depends on the input being clean at that instant — any noise gets digitised right along with the signal.
An integrating ADC does the opposite: it averages the input over a long time window. Random noise (white noise, 50/60 Hz mains hum) averages out almost completely, leaving the slow-moving DC component. This is what makes the dual-slope ADC the architecture of choice for digital multimeters and panel meters.
17.2 The dual-slope ADC
Phase 1 — fixed time T1 (integrate the input)
Switch the integrator to V_in for exactly T1 seconds (e.g. 2^N clocks of an internal counter). The integrator output ramps up at a rate proportional to V_in:
V_int after T1 = − (V_in / RC) · T1Phase 2 — integrate down with a known reference until V_int crosses zero
Switch the integrator to −V_ref. The integrator now ramps back toward zero at a rate proportional to V_ref. The time T2 to reach zero is proportional to V_in / V_ref:
T2 = T1 · (V_in / V_ref)So if you count clock cycles during T2, you get a digital number proportional to V_in.
Two-phase timing diagram
Why it rejects noise
If the integration time T1 is set to an integer number of mains periods (e.g. 100 ms covers both 50 Hz and 60 Hz neatly), any noise at the mains frequency integrates to exactly zero over T1. That is "normal-mode rejection" — and is the reason every 6½-digit DMM uses dual-slope.
Performance summary
| Dual-slope | |
|---|---|
| Conversion time | T1 + T2 ≈ 100 ms (slow) |
| Resolution | 16 – 24 bits typical |
| Linearity | Excellent (limited by integrator + comparator offsets) |
| Noise rejection | Outstanding for periodic noise at 1 / T1 and its harmonics |
A canonical dual-slope chip — ICL7106
The Intersil ICL7106 is a 3½-digit dual-slope ADC integrated with a LCD driver. It is the brain of every cheap pocket multimeter you have ever owned. Add four resistors, a few caps and a quartz crystal — and you have a working DMM.
17.3 The voltage-to-frequency (V/F) converter ADC
To digitise V_in, simply count the output pulses for a fixed time T:
Digital code = f_out · T ∝ V_inHow a V/F converter works
- V_in charges an integrator capacitor.
- When the integrator output crosses a threshold, a fixed-charge pulse is subtracted.
- The number of subtractions per second is proportional to V_in.
Pros
- Extremely high noise rejection — the V/F is itself an integrator.
- Isolation is trivial: drop an opto-coupler in the digital pulse train.
- Naturally produces a serial digital signal that can be carried hundreds of metres on twisted pair.
Cons
- Conversion time is set by the gate time T → typically tens of ms.
- Linearity is limited by the V/F itself, not by quantization.
17.4 The voltage-to-time (V/T) converter ADC
A V/T is essentially a single-slope ADC: charge a capacitor at a fixed current, measure how long it takes to reach V_in. The time-to-digital part is the counter.
Single-slope architecture is rarely used standalone because it depends on absolute capacitor + current accuracy. It survives inside time-to-digital converters (TDCs) used in laser ranging and very-high-resolution timing instruments.
17.5 Putting it all together
For exam-style questions, remember:
- Dual-slope is the answer when the keyword is "high resolution + good noise rejection + slow signal".
- V/F is the answer when the keyword is "isolation" or "long-distance transmission".
- V/T is the answer when the keyword is "time-to-digital conversion".