18.1 ADC specifications you must be able to read off a datasheet

Resolution (N bits)

The number of distinct output codes is 2^N. Resolution alone does not guarantee accuracy — a noisy 12-bit ADC can be effectively less accurate than a clean 10-bit one.

Quantization error

±½ LSB = ±(V_ref / 2^{N+1}). The unavoidable minimum error of any quantiser.

Differential Non-Linearity (DNL)

The deviation of each code step from the ideal width Q. DNL < 1 LSB means no missing codes.

Integral Non-Linearity (INL)

The cumulative deviation from a best-fit straight line through the transfer curve. A spec of INL < 1 LSB over full scale is excellent.

Conversion time / sampling rate

• Conversion time T_c — time from "start conversion" to "result ready".
• Sampling rate f_s — samples per second, often 1 / T_c for non-pipelined ADCs.

Effective Number of Bits (ENOB)

Real-world resolution, derated for noise and distortion:

   ENOB = (SINAD − 1.76) / 6.02

A 12-bit ADC with SINAD = 68 dB has ENOB = 11.0 — you only really get 11 useful bits.

Aperture jitter / SNR

For high-speed ADCs the sample-clock jitter sets a hard SNR ceiling:

   SNR_max  ≈  20 · log₁₀ ( 1 / (2π · f_in · t_j) )   dB

ADC specification summary table

18.2 Example ADC ICs — datasheet tour

ADC0804 — 8-bit, single-channel, SAR

• Successive approximation, internal clock from one external RC.
• ±¼ LSB linearity, ~100 µs conversion at 640 kHz internal clock.
• Single-ended 0–5 V input, parallel 8-bit output, interrupt pin.
• The classic introductory ADC for microcontroller projects.

ADC0808 / ADC0809 — 8-bit, 8-channel, SAR

• Same SAR core as ADC0804, with an 8-channel analog multiplexer in front.
• Three address inputs (ADD-A, B, C) pick the active channel.
• Used to read up to 8 sensors with one ADC.

ICL7106 — 3½-digit dual-slope

• Drives a 3½-digit LCD directly.
• ±1 LSB accuracy, ~3 conversions/second.
• Foundation of every $5 multimeter.

Modern microcontroller ADCs

• STM32F4 internal ADC: 12-bit SAR, 2.4 MSPS, 16-channel mux.
• ESP32 internal ADC: 12-bit SAR, two ADC blocks, integrated touch.
• AVR (Arduino) internal ADC: 10-bit SAR, 8-channel mux, ~15 kSPS.

18.3 Quick architecture decision tree

18.4 Course summary

You now have, in one place, the five pillars of Digital Electronics-II:

1. Logic families (Unit I). TTL is fast and current-hungry; CMOS is low-power and voltage-friendly; Schottky kills the saturation delay; interfacing requires noise-margin and current-budget checks; tri-state lets you build busses.
2. Semiconductor memories (Unit I extension). SRAM caches need 6T cells and speed; DRAM main memory uses 1T1C and refresh; ROM/EEPROM/Flash store firmware; PLA is the simplest programmable logic.
3. Combinational design (Unit II). Add/subtract using one adder, BCD-correct it with +6, speed it up with carry-look-ahead, build an ALU as a 1-bit slice replicated, decode/encode with priority encoders and BCD-to-7-segment drivers, and minimise any Boolean function with Quine–McCluskey when K-maps run out of dimensions.
4. Sequential design (Unit III). Ripple counters are cheap but glitchy; synchronous counters are clean but bigger; ring counters give one-hot states free; sequence generators produce arbitrary patterns from a shift register + feedback; asynchronous sequential design fits very fast, very small handshake circuits.
5. A/D conversion (Unit IV). Quantization sets the hard floor on accuracy; flash gives speed; SAR gives the best speed/resolution/area tradeoff; counting is the simplest with a DAC; dual-slope wins on noise rejection; V/F enables isolation; specifications (DNL, INL, ENOB, jitter) tell you what an ADC will really deliver.

18.5 Course outcomes — what you can now do

1. Design and analyse combinational logic circuits — adders, subtractors, comparators, code converters, encoders, decoders, ALUs.
2. Apply digital logic-family knowledge — pick between TTL and CMOS, interface them safely, and reason about timing, fan-out and noise margins. Recall the basics of semiconductor memory (SRAM, DRAM, ROM, EEPROM, Flash, PLA) for any system you build.
3. Design and analyse synchronous sequential logic circuits — arbitrary-modulus counters, sequence generators, ring and Johnson counters, state-machine controllers.
4. Design various converters — pick the right ADC architecture (flash, SAR, counting, dual-slope, V/F, V/T) for a target speed, resolution and noise budget, and read a real ADC datasheet to verify your choice.

18.6 Reference books

1. Integrated Electronics — Millman & Halkias (Pearson)
2. Modern Digital Electronics — R. P. Jain (McGraw Hill, 2009)
3. Digital Logic and Computer Design — M. Morris Mano (Pearson India, 2016)
4. Fundamentals of Digital Circuits — A. Anand Kumar (Prentice Hall India, 2016)

You are now ready to tackle every section of the exam paper — and, much more importantly, to design the digital pieces of any embedded system you encounter in real engineering work.