12.1 Why synchronous beats asynchronous

In a synchronous counter, all flip-flops are clocked by the same clock signal. Each flip-flop's J, K (or D, T) inputs are driven by combinational logic that decides whether that bit should toggle on the next clock edge.

Because every bit changes simultaneously on the clock edge, there are no ripple delays and no decoder glitches. The price you pay is more combinational gates between the flip-flops; the reward is a clean, fast counter that can be used to drive other synchronous logic.

12.2 The four excitation tables — must memorise

The excitation table tells you what inputs to apply to get a desired (present → next) transition. This is the inverse of the characteristic table and is the only tool you need to design any synchronous sequential circuit.

SR excitation

D excitation

D = Q_next — the simplest excitation, which is why D flip-flops dominate modern register-transfer design.

J-K excitation

J-K excitation has the most don't-cares, which gives the smallest K-maps and the fewest gates — that is why classical counter designs almost always start from J-K.

T excitation

T = Q XOR Q_next.

12.3 The J-K toggle rule for binary counters

For a counter, we want bit i to toggle exactly when every lower bit is 1 (because that is precisely when carrying happens in binary). So:

    J_0 = K_0 = 1
    J_1 = K_1 = Q_0
    J_2 = K_2 = Q_0 · Q_1
    J_3 = K_3 = Q_0 · Q_1 · Q_2

12.4 Standard synchronous counter ICs

All of these have a Ripple-Carry-Out (RCO) pin that asserts on the terminal count — perfect for chaining several chips into a 8-, 12-, or 16-bit synchronous counter without re-introducing ripple delays.

12.5 Designing an arbitrary synchronous sequence — the 5-step recipe

12.6 Worked example — synchronous counter with sequence 0, 1, 3, 2, 6, 7, 5, 4, 0, …

This is a 3-bit Gray code counter — adjacent codes differ in exactly one bit.

Step 1 — state table

Step 2 — excitation table for J-K flip-flops

Apply the J-K excitation rule to every transition above to get six K-maps (J0, K0, J1, K1, J2, K2).

Step 3 — minimised input equations (one possible solution)

    J0 = Q2' Q1' + Q2 Q1     K0 = Q2 Q1' + Q2' Q1
    J1 = Q0 Q2'              K1 = Q0' Q2
    J2 = Q1 Q0'              K2 = Q1' Q0

Each FF has only one or two AND gates feeding its J or K. The resulting circuit is compact and runs glitch-free at full clock rate.

12.7 Synchronous clear and synchronous load

The 74LS161/162/163 series provide two extra inputs that are synchronous (sampled on the clock edge), not asynchronous:

• Synchronous CLEAR (SR): When LOW at the clock edge, the count goes to 0 on that edge. This avoids the asynchronous-clear glitch that ruins a ripple counter's mod-N implementation.
• Synchronous LOAD (LD/PE): When LOW at the clock edge, the counter loads the value present on P0–P3 instead of incrementing.

Modulo-N counter using synchronous LOAD

Wire the RCO pin into LD; preload (2^N − M) into P0–P3. The counter then wraps every M clocks. Example: a 74LS163 with PI = 0110 preloaded becomes a divide-by-10 counter.

This is the cleanest way to build any modulus from a binary synchronous counter — no asynchronous clear, no decode glitches, runs at the full chip rate.

12.8 Cascading synchronous counters

Connect every chip to the same clock and chain their RCO outputs into the count-enable (ENP, ENT) inputs of the next chip. The next chip is only enabled in the clock cycle after RCO goes HIGH — preserving full synchronous operation.

This is exactly how every modern programmable counter / timer is built.