11.1 Flip-flop refresher — the four standard types

Every sequential circuit in this course is built from one of four flip-flops. The characteristic table tells you Q_next given the inputs.

SR flip-flop

D flip-flop

The simplest of all — Q follows D on the next clock edge.

J-K flip-flop

J-K fixes the SR ambiguity by toggling on the 1-1 input.

T flip-flop

T = J = K is the natural "toggle" flip-flop — the workhorse of binary counters.

11.2 What makes a circuit "sequential"?

A combinational circuit's output depends only on its current inputs. A sequential circuit's output depends on the current inputs and its internal state. The state lives in flip-flops, which means sequential circuits have memory.

The simplest sequential circuit is a single T flip-flop — every clock edge flips its Q output between 0 and 1. Cascade a few of those and you have a counter, the foundational building block of Unit III.

11.3 Ripple counter — the asynchronous shape

In an asynchronous (ripple) counter, the clock signal drives only the first flip-flop. Each subsequent flip-flop is clocked by the previous flip-flop's output.

For a 4-bit binary counter, the state sequence cycles through 0000, 0001, …, 1111, 0000.

4-bit ripple counter state table

11.4 The 74LS93 4-bit ripple counter

The 74LS93 packs four ripple-stage J-K flip-flops in one DIP-14:

• FF0 is independent — drives outputs Q0 (÷ 2 of the clock you wire to CKA).
• FF1, FF2, FF3 form a divide-by-8 chain — clocked at CKB.
• Wire Q0 → CKB and the chip is a divide-by-16 counter.
• Two MR (master reset) inputs combine into an AND so you can reset on a programmed state.

11.5 The ripple-counter propagation problem

Every stage adds its own propagation delay (t_pd) to the chain. So the highest-order bit lags the first stage by (N−1) × t_pd. In a 4-bit ripple counter with t_pd = 10 ns, Q3 settles 30 ns after the clock edge.

That is harmless if you only look at the counter on its own. But it is a real problem if you decode the counter outputs combinationally — during the transition window, the decode logic sees several incorrect states briefly. Those are called glitches, or transient false outputs.

11.6 Mod-N counters — chopping the sequence short

An N-bit ripple counter naturally cycles through 2^N states. To make it stop at state M and reset to 0, feed the binary value of M into a NAND gate connected to the asynchronous clear (CLR) inputs of all flip-flops.

Example: mod-10 (decade) ripple counter

You want 0000, 0001, …, 1001, then back to 0000 (skipping 1010–1111).

    Q3 ──┐
         ├── NAND ──► CLR (active LOW) of every FF
    Q1 ──┘

When Q3·Q1 = 1 — i.e. state 1010 — the NAND goes LOW and clears every FF asynchronously. The counter therefore stays in 1010 for only a few ns before snapping back to 0000.

This trick is how the 74LS90 (a divide-by-10 ripple counter on a single chip) works internally — and how the 74LS93 is configured for mod-10 use.

11.7 Worked example — design a mod-12 ripple counter

You want the sequence 0000, 0001, …, 1011, 0000.

1. N = ⌈log₂ 12⌉ = 4 → use four T flip-flops or one 74LS93.
2. M (the "stop and reset" state) = 12 → binary 1100.
3. Wire Q3·Q2 into a NAND → output drives the CLR pins of all four FFs.

The counter now cycles through 12 states.

11.8 Down-counting ripple counter

Take the complementary output Q̅ of each flip-flop as the clock for the next stage. The chain counts down — 1111, 1110, …, 0000, 1111.

11.9 Ripple counter — pros and cons

For most modern designs we therefore prefer synchronous counters (next lesson), which share one clock across all stages and thus produce all bits in lockstep.