13.1 The plain ring counter
A ring counter is a shift register whose serial output is fed back into its serial input. Initialise it with a single 1 followed by zeros and that 1 walks endlessly around the ring.
4-stage ring counter state table
| Pulse # | Q3 | Q2 | Q1 | Q0 |
|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 0 | 1 |
| 4 | 1 | 0 | 0 | 0 (back to start) |
For a 4-stage ring the sequence is 1000, 0100, 0010, 0001, 1000, … — one output is HIGH at any time, so a ring counter is also called a one-hot counter.
Disadvantage
The ring counter has only N distinct states for N flip-flops — far fewer than the 2^N a binary counter offers. The trade is zero decoding logic.
13.2 The Johnson (twisted-ring) counter
A small variation: feed the complement of the last stage back to the input, not the true output.
4-stage Johnson counter state table
| Pulse # | Q3 | Q2 | Q1 | Q0 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 0 |
| 3 | 1 | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 | 1 |
| 5 | 0 | 1 | 1 | 1 |
| 6 | 0 | 0 | 1 | 1 |
| 7 | 0 | 0 | 0 | 1 |
| 8 | 0 | 0 | 0 | 0 (cycle) |
So N flip-flops give 2N states — twice the ring counter, still with very simple decoding (each state can be detected with a 2-input gate). The Johnson counter is widely used as a timing generator in oscilloscopes and as a divider for sinusoidal-stepped waveforms.
13.3 Sequence generator from a shift register
A sequence generator produces a fixed binary pattern (e.g. 1011000101…) bit-by-bit. The general design uses a shift register fed by combinational logic over its stages — the structure of a linear feedback shift register (LFSR) with the right tap pattern.
Recipe
- Decide the period P of the sequence.
- Use
N = ⌈log₂ P⌉flip-flops. - Write a state table mapping each state to the next bit you want at the serial output.
- Treat that as a sequential-circuit design problem (excitation table → K-maps) and synthesise the feedback gates.
Modern designers most often pick maximal-length LFSRs for this job because they produce pseudo-random sequences of period 2^N − 1 with one XOR gate of feedback — the basis of every CDMA spread code, every cheap PRBS pattern generator on an oscilloscope, and every CRC checker.
13.4 Special counter ICs — quick tour
| Chip | What it is |
|---|---|
| 74LS90 | Asynchronous decade ripple counter — divide-by-2 stage + divide-by-5 stage, connect them externally to get ÷ 10 |
| 74LS92 | Asynchronous divide-by-12 ripple counter |
| 74LS93 | Asynchronous divide-by-16 ripple counter |
| 74LS160 / 161 / 162 / 163 | Synchronous 4-bit BCD / binary counters with synchronous load |
| 74LS190 / 191 | Synchronous BCD / binary up/down counters with one up/down control |
| 74LS192 / 193 | Synchronous BCD / binary up/down counters with separate UP and DOWN clocks |
| CD4017 | Decade Johnson counter with ten decoded outputs — beloved of hobby blinker circuits |
| CD4040 | 12-stage ripple binary counter — gives divide-by-2 through divide-by-4096 in one DIP |
| 74LS164 | 8-bit serial-in / parallel-out shift register — useful base for ring counters |
13.5 Asynchronous sequential counters
Not every state machine is clocked. Asynchronous sequential circuits change state in response to input changes, not a clock edge.
Why bother
- Speed. No clock means no clock period to wait for — the circuit reacts in just a few gate delays.
- Low power. No clock tree to drive.
- Simplicity for tiny circuits like a single push-button debouncer or a small handshake controller.
Why they are hard
- Hazards and races. When two inputs change "at the same time", the order in which the gates respond depends on tiny propagation-delay differences — sometimes the circuit reaches a wrong state.
- Stable / unstable states. Each row of the flow table must have at least one stable state; you have to design every transition so it terminates at a stable state without oscillation.
Classical design flow (Huffman style)
The most common practical examples of asynchronous sequential design are arbiter circuits, pulse synchronisers, edge detectors and bus handshake controllers.
13.6 When to pick which counter
| Need | Best choice |
|---|---|
| Small, low-power, decoders allowed | Asynchronous ripple counter (74LS93) |
| High-speed decoded outputs | Synchronous (74LS161/163) |
| Need one-hot outputs / state indicator | Ring counter or CD4017 |
| Need 2N states with simple decoding | Johnson counter |
| Need a pseudo-random pattern | Maximal-length LFSR |
| Need an arbitrary fixed pattern | Sequence generator (small state machine) |
| Asynchronous handshake / sub-ns response | Asynchronous sequential design |
Pick the simplest counter that solves the problem — the more complex the structure, the more pins, glue logic and clock-domain headaches it brings.