3.1 The TTL story in one sentence
Transistor–Transistor Logic (TTL) is a bipolar logic family in which the input is fed to the multi-emitter transistor of a transistor, and the output is taken from a totem-pole pair of transistors. It was the dominant logic family from the mid-1960s into the 1990s and still appears today on lab kits and legacy boards.
3.2 The standard 7400-series NAND gate
Input stage — the multi-emitter transistor (Q1)
Q1 has as many emitters as the gate has inputs. If any one input is LOW, that emitter forward-biases the base–emitter junction, pulling Q1's base low and starving Q2's base of current → Q2 and Q4 turn OFF → Q3 turns ON → output goes HIGH.
If all inputs are HIGH, current flows into Q1's collector (through its reverse-biased base–emitter junctions in the wrong direction, exploiting the parasitic base–collector PN), turning Q2 on hard, which turns Q4 on and Q3 off → output goes LOW. That is exactly NAND behaviour.
TTL NAND voltage-level truth table
| A (V) | B (V) | Q1 state | Q2 state | Q3 | Q4 | Y (V) | Logic |
|---|---|---|---|---|---|---|---|
| 0.2 (LOW) | 0.2 (LOW) | ON (forward) | OFF | ON | OFF | ~3.4 | HIGH (1) |
| 0.2 (LOW) | 5.0 (HIGH) | ON (forward) | OFF | ON | OFF | ~3.4 | HIGH (1) |
| 5.0 (HIGH) | 0.2 (LOW) | ON (forward) | OFF | ON | OFF | ~3.4 | HIGH (1) |
| 5.0 (HIGH) | 5.0 (HIGH) | Reverse-biased | ON (sat) | OFF | ON (sat) | ~0.2 | LOW (0) |
Output stage — the totem-pole
The output is a stack of two transistors (Q3 on top, Q4 on bottom) sharing one node. Only one of them is on at a time, so the output is either actively pulled up or actively pulled down. That is why TTL totem-pole outputs are fast — they don't depend on a pull-up resistor to charge load capacitance.
⚠️ Never tie two totem-pole outputs together. If one tries to drive HIGH while the other drives LOW, you get a direct Vcc-to-GND short through Q3 of one chip and Q4 of the other. Use open-collector or tri-state outputs for any kind of wired-OR / bus operation.
3.3 TTL DC characteristics worth memorising
| Parameter | Min | Typ | Max |
|---|---|---|---|
| V_IH (input HIGH) | 2.0 V | — | 5.0 V |
| V_IL (input LOW) | 0 V | — | 0.8 V |
| V_OH (output HIGH) | 2.4 V | 3.4 V | — |
| V_OL (output LOW) | — | 0.2 V | 0.4 V |
| I_IH (input HIGH current) | — | — | 40 µA |
| I_IL (input LOW current) | — | — | 1.6 mA (into the source!) |
| Fan-out (similar gates) | 10 | ||
| Propagation delay | — | 10 ns | — |
| Supply Vcc | 4.75 V | 5.0 V | 5.25 V |
The interesting bit is I_IL = 1.6 mA flowing OUT of the input pin into whatever is driving it. That is why a TTL gate driving another TTL gate is best at sinking current, not sourcing it — and it shapes how every other family must interface to TTL.
3.4 The "saturation problem" — why standard TTL is slow
Inside Q4 of the standard 7400 gate, the transistor is driven into deep saturation when the output is LOW. That stores excess minority carriers in the base. When the gate needs to switch back to HIGH, those carriers have to be swept out first — adding a storage delay of several nanoseconds.
In a typical 7400 gate this storage delay dominates t_PHL. If we can stop the transistors from saturating, we can switch faster — and that is exactly what Schottky TTL does.
3.5 Schottky TTL — the speed upgrade
A Schottky diode is a metal-semiconductor junction with a forward voltage of about 0.3 V (versus ~0.7 V for a normal PN diode) and effectively no minority carrier storage. In Schottky TTL, every saturating transistor has a Schottky diode connected between its base and collector — a so-called Schottky-clamped transistor.
When the transistor tries to saturate (V_BE ≈ 0.7 V, V_CE → 0.2 V), the diode forward-biases and shunts the excess base current straight to the collector. The transistor never quite reaches saturation, so there is no storage delay when it switches off.
3.6 Variants of the Schottky family
| Sub-family | Symbol | t_pd | Power / gate | Notes |
|---|---|---|---|---|
| Standard Schottky | 74S | ~3 ns | 19 mW | First Schottky-clamped TTL; fast but power-hungry |
| Low-power Schottky | 74LS | ~9 ns | 2 mW | The "default" TTL for the 1980s/90s — best power/speed tradeoff |
| Advanced Schottky | 74AS | ~1.5 ns | 8 mW | Successor to 74S |
| Advanced Low-power Schottky | 74ALS | ~4 ns | 1 mW | Successor to 74LS |
| Fairchild Advanced Schottky TTL | 74F | ~3 ns | 4 mW | Fast and reasonably low-power |
3.7 Other useful TTL output structures
Open-collector outputs (74LS01, 74LS05 …)
Q3 is removed; only Q4 remains. The user adds an external pull-up resistor to Vcc.
- Multiple open-collector outputs can be tied together to form a wired-AND (if any output is LOW, the line is LOW). Useful for one-wire interrupt lines on a bus.
- The external resistor lets you pull the line up to a different voltage — handy for driving relays, LEDs or higher-voltage logic.
Tri-state (three-state) outputs (74LS244, 74LS245 …)
Adds a third state — High-Z (high impedance) — controlled by an "output enable" pin. Covered in the next lesson; this is the modern way to share a bus.
3.8 Practical pitfalls
- Unused TTL inputs float HIGH — but only weakly. In a noisy environment, always tie them to Vcc through a 1 kΩ resistor (not directly, to limit transient current) or to a known logic level.
- Vcc bypass capacitors are not optional. Place a 0.1 µF ceramic close to every TTL IC; the fast totem-pole switching pulls big transient currents and will corrupt logic levels across a board without bypass.
- TTL inputs sink, not source, current. Anything driving a TTL input must be able to sink ~1.6 mA from each input — easy for another TTL chip, harder for a slow CMOS chip running at low Vcc.
- Schottky clamping increases input current slightly (~0.4 mA vs 1.6 mA for std TTL) — easier for CMOS or 3.3 V parts to drive.