2.1 Why FETs matter in digital electronics

Bipolar Junction Transistors (BJTs) were the first switching devices and still dominate older TTL ICs. Modern digital ICs — including almost every microcontroller, FPGA and memory you will use — are built from Field Effect Transistors (FETs). The reason is one number: input current.

A BJT draws base current the whole time it is "on". A FET, by contrast, is controlled by voltage on a capacitor-like gate, so its steady-state input current is essentially zero. That single fact is what makes very large CMOS chips like multi-billion-transistor SoCs possible.

2.2 The FET family tree

2.3 NMOS / PMOS as switches

A MOSFET operates in three regions, but for digital logic we only care about two of them:

• Cut-off: Vgs < Vth → the channel does not exist → the transistor is essentially an open switch.
• Saturation (deep triode for logic): Vgs >> Vth → the channel is fully formed → the transistor is essentially a closed switch with a small on-resistance.

In digital design we deliberately avoid the linear/active region in between, where the transistor would behave like a controlled resistor and dissipate power.

NMOS truth table (as a switch)

PMOS truth table (as a switch)

Key insight: NMOS turns ON for a HIGH input, PMOS turns ON for a LOW input. They are complementary — exactly what makes CMOS work.

2.4 The CMOS inverter — the canonical building block

At any given moment only one of the two networks conducts, so almost no static current flows from Vdd to GND. That is why CMOS has near-zero static power dissipation — a defining feature.

2.5 What "digital IC characteristics" means

When you read a digital IC datasheet, the same dozen parameters keep appearing. These are the figures of merit you must be able to define, compare across families, and use to predict whether a circuit will actually work.

Voltage levels

Noise-margin diagram

The "safety zone" between what an output produces and what the next input is willing to accept:

    NM_H = V_OH(min) − V_IH(min)     // safety margin for logic 1
    NM_L = V_IL(max) − V_OL(max)     // safety margin for logic 0

A larger noise margin means the chip is more tolerant of supply ripple, ground bounce and EMI. CMOS typically has a noise margin around 30 % of Vdd; standard TTL has only ~0.4 V at the low side — which is exactly why CMOS is preferred in noisy industrial environments.

Fan-in and fan-out

• Fan-in: Number of inputs a single gate has. Limited by the way pull-up/pull-down stacks add up.
• Fan-out: Number of similar gate inputs a single output can drive without leaving its valid logic range.

For TTL, typical fan-out is 10. For CMOS, fan-out is effectively unlimited at DC (gates draw no static current) but drops at high frequency because every driven gate adds capacitance to the output.

Propagation delay (t_pd)

The time between a change at the input and the resulting change at the output, measured at the 50 % crossing point. Often broken into:

• t_PHL — delay when output goes from HIGH to LOW
• t_PLH — delay when output goes from LOW to HIGH

Total propagation delay through a chain of N gates ≈ N × t_pd. This is what limits the maximum clock frequency of a circuit.

Power dissipation

• Static power: drawn even when nothing is switching. Negligible for pure CMOS; significant for TTL.
• Dynamic power: P = C × Vdd² × f — proportional to switching frequency. Dominates in modern high-speed CMOS.

Speed-power product

Single figure of merit that combines speed and power:

    Speed × Power product = t_pd × P_d   (units: pJ)

Lower is better. Used to compare logic families across very different operating points.

2.6 Comparison snapshot

These four numbers are what you should remember as a "smell test" the next time you see an IC: family, speed, noise margin, power.