4.1 The CMOS inverter revisited
A single CMOS inverter contains exactly two MOSFETs: one PMOS connected to Vdd and one NMOS connected to GND, sharing both gate and drain. Recap from lesson 2:
| Vin | PMOS Mp | NMOS Mn | Vout |
|---|---|---|---|
| 0 (LOW) | ON | OFF | Vdd (HIGH) |
| Vdd (HIGH) | OFF | ON | 0 (LOW) |
4.2 NAND and NOR in CMOS
Every CMOS logic gate is built by duality:
- To pull the output LOW when the gate's logic should produce 0, use a NMOS network of the same shape (series for AND, parallel for OR).
- To pull the output HIGH when the logic should produce 1, use a PMOS network of the dual shape (parallel for AND, series for OR).
CMOS NAND truth table — with FET states
| A | B | PMOS Mp1 (A̅) | PMOS Mp2 (B̅) | NMOS Mn1 (A) | NMOS Mn2 (B) | Pull-up path? | Pull-down path? | Y |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | ON | ON | OFF | OFF | YES (both PMOS open) | NO | 1 |
| 0 | 1 | ON | OFF | OFF | ON | YES (Mp1) | NO (Mn1 open) | 1 |
| 1 | 0 | OFF | ON | ON | OFF | YES (Mp2) | NO (Mn2 open) | 1 |
| 1 | 1 | OFF | OFF | ON | ON | NO (both PMOS closed) | YES (series NMOS) | 0 |
That is exactly the NAND truth table. Notice that in every row one of the pull-up and pull-down networks is "closed off" — so almost no current flows from Vdd to GND. The brief overlap during the switching transition is the only source of dynamic power dissipation.
4.3 Why CMOS is the dominant family today
| Property | CMOS | TTL |
|---|---|---|
| Static power dissipation | ≈ 0 (only leakage) | ~10 mW per gate |
| Supply voltage range | 1.8 V – 15 V | strictly 5 V ± 5 % |
| Noise margin | ~30 % of Vdd | ~400 mV |
| Input current at DC | a few pA | up to 1.6 mA |
| Speed (modern HCMOS / AC) | comparable to LS-TTL | faster than 4000-series CMOS |
| Density (gates / mm²) | very high | low |
CMOS scales to billions of transistors on one die because each gate consumes power only while switching — not while idle. That is why every microcontroller, FPGA, GPU and memory IC made today is CMOS internally.
4.4 The two practical problems when mixing TTL and CMOS
If you have, say, a TTL output driving a CMOS input, two things may go wrong:
- Voltage mismatch. A standard 4000-series CMOS gate running at Vdd = 5 V wants V_IH(min) ≈ 3.5 V. A standard TTL output guarantees only V_OH(min) = 2.4 V. That gap means the CMOS input may read the TTL HIGH as somewhere between HIGH and LOW — exactly the "bad" zone you must never use.
- Current mismatch. A TTL input demands up to 1.6 mA in the LOW state. A CMOS output can usually source only a few hundred µA, so connecting a CMOS gate directly to a TTL input may not be able to pull it cleanly LOW.
The fix is to insert a small interface circuit. The exact circuit depends on which direction you are going.
4.5 Interfacing decision tree
TTL output → CMOS input (same Vdd = 5 V)
Add a pull-up resistor (typically 4.7 kΩ) from the TTL output to Vcc. The TTL output can sink current to pull LOW; the pull-up brings the HIGH level up to a clean 5 V.
CMOS output → TTL input (same supply)
For HCMOS / 74HC the output current is enough to drive one or two TTL-LS inputs directly. For 4000-series CMOS at low frequency, use a CMOS buffer (e.g. 4049) or a level-translator IC if you need to drive multiple TTL inputs.
Different supply voltages (e.g. 3.3 V CMOS ↔ 5 V TTL)
Use a dedicated level translator — typified by the 74LVC or TXS01xx families — or an open-drain output with a pull-up to the higher supply. Never connect a 5 V signal directly to a 3.3 V CMOS input; modern thin-gate inputs are damaged by anything above Vdd + 0.3 V.
4.6 Tri-state (three-state) logic
A normal logic output has two states: HIGH or LOW. A tri-state output adds a third state — High-Z, in which the output transistor is electrically disconnected from the pin.
Tri-state buffer truth table (active-low OE)
| OE̅ | Input A | Output Y | Driver state |
|---|---|---|---|
| 0 | 0 | 0 | Active LOW |
| 0 | 1 | 1 | Active HIGH |
| 1 | 0 | Z | High-Z (output floating) |
| 1 | 1 | Z | High-Z (output floating) |
When Enable = 1, the gate behaves normally and drives HIGH or LOW. When Enable = 0, both the pull-up and pull-down transistors are off — the output is "floating", a high impedance.
Why tri-state matters
It is what makes shared buses physically possible. On a typical microprocessor data bus, many devices share the same wires. At any instant, exactly one device must be enabled to drive the bus; all the others are in High-Z so they do not fight the active driver.
A canonical tri-state buffer — the 74LS244
The 74LS244 is an 8-bit unidirectional tri-state buffer with two enable lines (one for each half). It is used everywhere as an "input buffer" or "address bus driver". Its truth table is the same as the buffer above but for 8 bits in parallel.
The 74LS245 is its bidirectional cousin and is the most common transceiver on classic 8-bit busses.
Tri-state vs open-collector — which to use?
| Open-collector | Tri-state | |
|---|---|---|
| Pull-up | External resistor required | Active PMOS inside the chip |
| Wired logic | Yes (wired-AND) | No — only one driver may be enabled |
| Speed | Slower (RC of pull-up) | Fast — active drive both ways |
| Typical use | Interrupt lines, I²C, status flags | Shared address/data busses, multi-master peripherals |
4.7 Quick checklist before connecting two chips
- Do they share a ground? (They must!)
- Are the supply voltages compatible, or do you need a level translator?
- Is the driving output's V_OH ≥ the receiver's V_IH and V_OL ≤ V_IL?
- Can the driver supply the input current required by all receivers in parallel? (Fan-out check.)
- If they share a bus, is exactly one driver enabled at any time, with all others in High-Z?
If you can tick all five, the interface will be reliable across temperature and supply variations.