5.1 Why this lesson exists
The four units in the syllabus list flow naturally, but Course Outcome 2 explicitly says the student must "acquire basic knowledge of digital logic families & semiconductor memories". Memories are not in the unit list, but they share the same FET building blocks as the logic families just covered — and you cannot read an ADC datasheet, design an embedded system, or wire a microcontroller bus without knowing what memory chip you are talking to. So this lesson sits at the end of Unit I to satisfy CO-2.
5.2 The memory taxonomy
| Class | Reads | Writes | Retains without power? | Typical use |
|---|---|---|---|---|
| SRAM | Fast (~ns) | Fast (~ns) | No | CPU caches, register files |
| DRAM | Fast (~10 ns) | Fast (~10 ns) | No (needs refresh every ~64 ms) | Main system memory |
| Mask ROM | Fast | One-time at fab | Yes | Firmware in mass-produced products |
| PROM | Fast | Once (fuse blown) | Yes | Field-programmable boot loaders |
| EPROM | Fast | UV erase + reprogram | Yes | Development prototyping |
| EEPROM | Fast | Slow (~5 ms / byte) | Yes | Configuration data |
| Flash | Fast | Slow erase block + write | Yes | SSDs, MCU program memory, USB drives |
5.3 Memory organisation — the address-data model
Every memory chip has the same external interface:
- Address lines A[n−1:0] select one of
2^nlocations. - Data lines D[m−1:0] carry the m-bit word at the selected location.
- Control lines — typically Chip Enable (CE̅), Output Enable (OE̅), and Write Enable (WE̅).
A "32 K × 8" chip has 15 address pins and 8 data pins → 32 768 bytes total.
5.4 SRAM — the 6-transistor cell
The cell is two cross-coupled inverters (M1/M2 and M3/M4) that hold one bit indefinitely as long as Vdd is applied. Two access transistors (M5, M6) connect the cell to a bit-line pair when the word line is asserted.
| Operation | Word line | Bit line | Bit line bar |
|---|---|---|---|
| Idle | 0 | floating | floating |
| Read | 1 | pre-charged, then drained by Q | pre-charged, then drained by Q̅ |
| Write 0 | 1 | drive 0 | drive 1 |
| Write 1 | 1 | drive 1 | drive 0 |
SRAM is fast (nanoseconds), but each cell needs 6 transistors → low density and high cost per bit. That is why SRAM is used only where speed matters most: CPU caches.
5.5 DRAM — the 1T1C cell
One transistor + one capacitor → just two devices per bit. Density is far higher than SRAM, but:
- The capacitor leaks → cell must be refreshed every ~64 ms by reading and rewriting every row.
- Reads are destructive — the bit line drains the capacitor → sense amplifiers must rewrite the cell after every read.
| Operation | Word line | Bit line | Notes |
|---|---|---|---|
| Read | 1 | sense amplifier reads | Then rewrite the cell |
| Write | 1 | drive new value | Capacitor charges/discharges |
| Refresh | 1 (entire row) | sense + rewrite | Done every ~64 ms |
DRAM gives you many gigabytes for a few rupees per gigabyte — but at the cost of refresh logic. Every system RAM you have ever owned is DRAM.
5.6 ROM types — a comparison
| Type | Write mechanism | Erase mechanism | Endurance | Typical use |
|---|---|---|---|---|
| Mask ROM | At fabrication (metal mask) | Cannot | 1 write | Firmware in millions of identical units |
| PROM | Fuse melting (electrical) | Cannot | 1 write | One-time programmable boot ROM |
| EPROM | High-voltage hot-electron injection | UV light (15 min, ~ 254 nm) | ~100 cycles | Old microcontroller firmware, EPROM emulators |
| EEPROM | Tunnelling (high V on control gate) | Tunnelling (byte-by-byte) | ~10⁶ cycles | MCU configuration / NV variables |
| Flash | Tunnelling (high V) | Block-erase | ~10⁴–10⁶ cycles | SSDs, MCU program memory, USB drives, eMMC |
Flash memory cells — NAND vs NOR
- NOR flash: Each cell connects directly to the bit line — random reads are fast. Used for MCU program memory (executed in place).
- NAND flash: Cells share a series stack — reads must fetch a whole page. Cheaper per bit; used for mass storage.
5.7 PLA — Programmable Logic Array
A PLA is a generic combinational circuit you can program to realise any sum-of-products function within its capacity. It has two programmable planes:
Compare with related programmable parts:
| Device | AND plane | OR plane | What you program |
|---|---|---|---|
| ROM | Fixed (full decoder) | Programmable | OR plane only — basically a truth-table lookup |
| PAL | Programmable | Fixed | AND plane only — fewer product terms, faster |
| PLA | Programmable | Programmable | Both — most flexible |
A PLA is used inside CPLDs and as the heart of microcoded control units. For modern designs we mostly use FPGAs, which generalise the same idea with look-up tables (LUTs) instead of an AND-OR plane.
5.8 Choosing the right memory
5.9 At-a-glance summary
| Memory | Cell size | Speed | Cost / bit | Retention |
|---|---|---|---|---|
| SRAM | 6T | ~1 ns | Highest | Volatile |
| DRAM | 1T + 1C | ~10 ns | Low | Volatile (refresh) |
| Mask ROM | 1T | ~10 ns | Lowest at scale | Permanent |
| EPROM | 1T (floating gate) | ~50 ns | Medium | ~10 yr |
| EEPROM | 2T (floating gate + access) | ~50 ns / 5 ms write | High | ~10 yr |
| Flash NOR | 1T (floating gate) | ~50 ns read | Medium | ~10 yr |
| Flash NAND | 1T (floating gate) | ~25 µs page read | Low | ~10 yr |