6.1 The half adder

A half adder adds two bits A and B and produces two outputs: a Sum bit S and a Carry-out bit C.

    S = A XOR B
    C = A AND B

It is called half because it has no provision for an incoming carry from a lower bit position — so by itself, it can only add the LSB column of a multi-bit number.

6.2 The full adder

A full adder has three inputs — A, B and Cin — and produces S and Cout. It is the building block of every multi-bit adder, including the one inside your CPU.

K-map minimisation gives:

    S    = A XOR B XOR Cin
    Cout = (A AND B) OR (Cin AND (A XOR B))

A common implementation is two half adders + an OR gate.

6.3 The ripple-carry adder

Cascade N full adders by feeding each stage's Cout into the next stage's Cin. The result is an N-bit ripple-carry adder:

This is conceptually clean but its worst-case delay grows linearly with N, because the highest-order Cout cannot settle until every stage below it has settled. For N = 32 bits that is 32 gate delays — too slow for modern CPUs. We will fix that in the next lesson with the carry-look-ahead adder.

6.4 The half subtractor

The half subtractor computes A − B of two bits and produces a Difference D and a Borrow Bo:

    D  = A XOR B
    Bo = NOT(A) AND B

6.5 The full subtractor — explicit truth table

The full subtractor extends the half subtractor with a Borrow-in (Bin) from the previous stage. Three inputs A, B, Bin; two outputs D, Bout.

K-map minimisation gives:

    D    = A XOR B XOR Bin
    Bout = (NOT(A) AND B) OR (Bin AND NOT(A XOR B))

But in practice we rarely build subtractors. Instead, we represent negative numbers in 2's-complement and re-use the adder:

    A − B  =  A + (2's complement of B)
           =  A + (NOT B) + 1

The "+ 1" is realised simply by tying the first stage's Cin to 1, and "NOT B" is realised by passing B through an XOR gate with the mode bit M. That gives the textbook adder/subtractor circuit:

That single mode bit converts an adder into a subtractor for free — which is why every CPU's ALU has exactly this shape.

6.6 BCD arithmetic — why it is needed and why it is hard

A BCD digit encodes one decimal digit (0–9) in 4 bits. So decimal 27 in BCD is 0010 0111. BCD is the natural format for anything that ultimately drives a decimal display (calculators, panel meters, point-of-sale terminals).

The trouble: if you add two BCD digits with a normal binary adder, the result might overshoot. For example,

        0110     (decimal 6)
      + 0111     (decimal 7)
      ──────
        1101     (decimal 13 in binary, but NOT a valid BCD digit!)

BCD only allows digit codes 0000–1001. Codes 1010–1111 are forbidden. We need to fix the sum.

6.7 The BCD adder rule

After a normal 4-bit binary addition, add 0110 (decimal 6) to the result whenever either:

1. The binary sum is greater than 9 (i.e. 1010–1111), OR
2. A carry-out occurred from the 4-bit add (i.e. result > 15).

That "correction" propagates a +1 into the next decimal digit (the carry-out of the corrected stage).

The detection logic is one OR gate fed by the original Cout and a small AND/OR network that recognises S = 1010 … 1111. The standard IC for this is the 74283 4-bit binary adder wired into a BCD adder block.

6.8 Worked example — BCD addition of 47 + 38

   47  →  0100 0111
   38  →  0011 1000

Stage 0 (units): 0111 + 1000 = 1111 (binary), which is > 9. Add 0110 → 0001 0101 ⇒ digit 5, carry 1.

Stage 1 (tens): 0100 + 0011 + 1 (carry) = 1000 (binary), which is ≤ 9 and no carry. No correction.

Final result: 1000 0101 ⇒ decimal 85, exactly as expected.

6.9 What we built — and what's next

In this lesson we built every kind of combinational arithmetic circuit you need for unsigned numbers — but the ripple-carry path is slow. The next lesson speeds it up with the carry-look-ahead adder, builds a serial adder for ultra-low-area arithmetic, and shows how all of this comes together inside an ALU.