8.1 What "MSI" means

SSI (Small-Scale Integration) chips have 1–10 gates per package — single gates, flip-flops. MSI (Medium-Scale Integration) packs roughly 10–100 gates per package — full functional blocks like 4-bit adders, comparators, multiplexers and parity generators. Most of the building blocks in this unit are MSI chips, and you will see the same part numbers appearing again in real designs.

8.2 The 4-bit magnitude comparator (74LS85)

A digital comparator decides whether two unsigned numbers A and B are equal, less than or greater than each other. For a 1-bit comparator:

    A=B  : (A XNOR B)                     = NOT(A XOR B)
    A>B  : A AND NOT B
    A<B  : NOT A AND B

1-bit comparator truth table

For a 4-bit comparator, equality means every bit pair must be equal. Greater-than is decided by the most significant differing bit. The 74LS85 implements this in one chip and gives three cascade inputs (A<B in, A=B in, A>B in) so multiple 74LS85s can be chained for 8-, 12-, 16-bit comparisons.

Cascade truth table for the most-significant chip

8.3 Parity checker / generator

Recall from the codes lesson: a parity bit is set so the total number of 1s in a word is even (even parity) or odd (odd parity).

Generator equations

    P_even = D3 XOR D2 XOR D1 XOR D0
    P_odd  = NOT (D3 XOR D2 XOR D1 XOR D0)

A chain of 3 XORs (or one 74LS86 quad XOR) makes a 4-bit even-parity generator. The 74LS280 is the standard 9-bit version used on classic memory boards.

Checker

At the receiver, XOR all data bits and the received parity bit. If the result is 0, parity is correct; if the result is 1, an error has been detected.

    Error = D3 XOR D2 XOR D1 XOR D0 XOR P_received

8.4 Code converters

A code converter is a combinational network that takes one code as input and produces another code as output. The design recipe is always the same:

1. Write the truth table mapping every input code to the corresponding output code.
2. Minimise each output bit independently using a K-map or the Q-M method.
3. Implement with gates (or a ROM / MUX for large tables).

8.4.1 Binary → Gray converter

For an N-bit word:

    G_{N-1} = B_{N-1}
    G_i     = B_{i+1} XOR B_i

8.4.2 BCD → Excess-3 converter — complete truth table

Minimising each E bit by K-map gives:

    E3 = D3 + D2·D1 + D2·D0
    E2 = D2'·D1 + D2'·D0 + D2·D1'·D0'
    E1 = D1·D0' + D1'·D0
    E0 = D0'

That is a small AND-OR network feeding from D3..D0 — the entire converter fits in one 74LS86 + 7400-family package.

8.4.3 Other useful code converters

8.5 Putting MSI pieces together — design recipe

For any combinational problem above ~8 inputs, the most productive design flow is:

1. Decompose the function into smaller pieces, each fitting a single MSI chip.
2. Pick the right MSI part — adder, comparator, mux, encoder, decoder, parity tree.
3. Wire enable / cascade pins so chips chain correctly (carry, A=B cascade, OE).
4. Reduce remaining glue logic by K-map or by replacing it with a MUX/ROM.

This is exactly the design style used in the entire 7400 family and is the pattern your exam will test.