9.1 Encoders — turning many lines into few
An encoder is the opposite of a decoder. It has 2^N inputs and N outputs; whichever single input is active, the output produces its binary index.
9.1.1 Simple 8-to-3 encoder
| D7 D6 D5 D4 D3 D2 D1 D0 | A2 A1 A0 |
|---|---|
| 0 0 0 0 0 0 0 1 | 0 0 0 |
| 0 0 0 0 0 0 1 0 | 0 0 1 |
| 0 0 0 0 0 1 0 0 | 0 1 0 |
| 0 0 0 0 1 0 0 0 | 0 1 1 |
| 0 0 0 1 0 0 0 0 | 1 0 0 |
| 0 0 1 0 0 0 0 0 | 1 0 1 |
| 0 1 0 0 0 0 0 0 | 1 1 0 |
| 1 0 0 0 0 0 0 0 | 1 1 1 |
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
Just three OR gates. The problem: what if more than one input is active at the same time? The simple encoder produces an incorrect output that is the OR of the encoded values — usually meaningless. We need a smarter version.
9.1.2 Priority encoder — the 74LS148
A priority encoder picks the highest-numbered input that is currently active and outputs its index. All lower-priority inputs are ignored.
Priority encoder truth table (active-low inputs, 74LS148-style)
| EI̅ | D7̅ | D6̅ | D5̅ | D4̅ | D3̅ | D2̅ | D1̅ | D0̅ | A2̅ | A1̅ | A0̅ | GS̅ | EO̅ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | × | × | × | × | × | × | × | × | 1 | 1 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 0 | 0 | × | × | × | × | × | × | × | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | × | × | × | × | × | × | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | × | × | × | × | × | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | × | × | × | × | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 0 | × | × | × | 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 0 | × | × | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | × | 1 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
EI̅ is the enable input, GS̅ asserts "any input active and chip enabled", EO̅ cascades into the next 74LS148's EI̅ — giving a 16-to-4 priority encoder out of two chips, and 32-to-5 out of four.
Priority encoders are central to interrupt controllers. Inside a microcontroller, every peripheral has an interrupt request line; a priority encoder converts them to a single vector telling the CPU which one to service first.
9.2 Decoders — turning few lines into many
A decoder is the inverse of an encoder. Its N inputs select exactly one of 2^N outputs.
74LS138 — 3-to-8 line decoder truth table
| E (enabled?) | S2 | S1 | S0 | Selected output |
|---|---|---|---|---|
| no | × | × | × | all HIGH |
| yes | 0 | 0 | 0 | Y0̅ = 0 |
| yes | 0 | 0 | 1 | Y1̅ = 0 |
| yes | 0 | 1 | 0 | Y2̅ = 0 |
| yes | 0 | 1 | 1 | Y3̅ = 0 |
| yes | 1 | 0 | 0 | Y4̅ = 0 |
| yes | 1 | 0 | 1 | Y5̅ = 0 |
| yes | 1 | 1 | 0 | Y6̅ = 0 |
| yes | 1 | 1 | 1 | Y7̅ = 0 |
Decoder applications
- Memory chip-select decoding. A microprocessor's address bus has high-order bits that pick which memory chip to enable. Wire those bits to a 74LS138; each Yi enables one chip. Address ranges are partitioned automatically.
- Function realisation as minterms. Any Boolean function can be written as the OR of its minterms; a 3-to-8 decoder produces all 8 minterms in parallel, and a single OR gate at the output gives the function. Useful when the function has many minterms.
- Demultiplexer. Tie one of the enable inputs to a single data line and you have a 1-to-8 demultiplexer — routing one input to one of eight outputs.
9.3 Display drivers — the BCD-to-seven-segment decoder
A seven-segment display shows decimal digits using seven LED segments labelled a–g. Each digit is a particular pattern:
a a a
f b Segments lit for "5": a, f, g, c, d
f b
g g g
e c
e c
d d d
Full BCD-to-7-segment truth table (common-cathode, active-HIGH)
| BCD | Decimal | a | b | c | d | e | f | g |
|---|---|---|---|---|---|---|---|---|
| 0000 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 0001 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 0010 | 2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 0011 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 0100 | 4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 0101 | 5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0110 | 6 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 0111 | 7 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| 1000 | 8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1001 | 9 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
A BCD-to-7-segment decoder/driver has four BCD inputs and seven outputs that drive the segments directly through current-limiting resistors. Two flavours:
| Chip | Display type | Output polarity |
|---|---|---|
| 74LS47 | Common-anode (LED cathodes are driven low) | Active LOW |
| 74LS48 | Common-cathode (LED anodes are driven high) | Active HIGH |
7447/7448 extras
- LT (lamp test) input — forces all seven segments on for a visible self-test.
- BI/RBO (blanking input / ripple blanking output) — turns the display off when forced LOW; chained between digits to suppress leading zeros (a "01234" 5-digit display shows " 1234").
- RBI (ripple blanking input) — paired with the previous digit's RBO so the leading-zero suppression "ripples" across the digits automatically.
9.4 Drivers vs decoders — what is the difference?
A pure decoder (74LS138) can output only standard logic-level currents — typically 4 mA, not enough to light an LED segment. A driver has a higher-current output stage, often open-collector or open-drain, capable of sinking 25–50 mA. The 74LS47 is a true driver — you wire its outputs directly to the LED cathodes through a small resistor and that is it. The "decoder" in BCD-to-7-segment "decoder/driver" tells you it has both functions in one chip.
9.5 Putting it all together — a digital voltmeter front panel
A complete 4-digit decimal display panel uses:
- Four BCD digits (from an ADC's output register).
- Four 74LS47 BCD-to-7-segment decoder/drivers — one per digit.
- Four common-anode 7-segment displays — wired in multiplex mode for low pin count.
- A 4-bit BCD counter (74LS90) and a small clock to scan one digit at a time, plus a 1-of-4 decoder (74LS139) to pulse the common anodes in sequence.
Everything in that block diagram is an MSI chip we have just met — and that is exactly the design style used on every cheap multimeter, calculator and panel meter you have ever owned.