3.1 The Instruction Cycle

Every instruction passes through the same master loop:

1. Fetch — read the instruction from memory into IR.
2. Decode — identify opcode and addressing mode.
3. (Optional) Fetch effective address — if the mode is indirect, read the pointer.
4. Execute — perform the operation.
5. Interrupt check — between instructions, service pending interrupts.

This loop repeats from power-on until halt. Micro-operations inside each phase are written in Register Transfer Language (RTL): R2 ← R1 means "copy contents of R1 into R2 on the next clock edge."

3.2 Timing Signals: Who Says "Now"?

A sequence counter (SC) feeding a decoder generates timing signals T0, T1, T2, … — exactly one is high per clock cycle:

Clock cycle :   1    2    3    4
T0          :   1    0    0    0
T1          :   0    1    0    0
T2          :   0    0    1    0
T3          :   0    0    0    1

A micro-operation labelled "T1: IR ← M[AR]" means the memory-read and IR-load control lines are asserted only while T1 is high. SC ← 0 resets the counter to begin the next instruction's fetch.

3.3 The Fetch–Decode Sequence in RTL

T0: AR <- PC              (address of next instruction to MAR/AR)
T1: IR <- M[AR],          (read instruction word)
    PC <- PC + 1          (point to next word ALREADY)
T2: D0..D7 <- decode IR(12-14),
    AR <- IR(0-11),       (address field ready)
    I  <- IR(15)          (indirect mode bit)

Why PC increments during T1, not after execute: the incremented PC is needed immediately if the instruction is two words long, and it lets fetch of the next instruction overlap wherever possible. Exam answers that increment PC "at the end" lose the subtlety.

If the instruction is a memory-reference type with I = 1 (indirect), one extra cycle dereferences the pointer:

T3: AR <- M[AR]           (indirect: fetch the real address)

3.4 Execute-Phase Examples

ADD:  T4: DR <- M[AR]          LDA:  T4: DR <- M[AR]
      T5: AC <- AC + DR,             T5: AC <- DR, SC <- 0
          SC <- 0
STA:  T4: M[AR] <- AC, SC <- 0
BUN:  T4: PC <- AR, SC <- 0    (unconditional branch)

Note the pattern: every execute sequence ends with SC ← 0, restarting the fetch. Register-reference and I/O instructions decode entirely from IR bits and execute in a single T3 step.

3.5 Control Signal Generation

The control unit converts (decoded opcode D0–D7, timing Ti, mode bit I, flags) into control functions. Each RTL statement corresponds to a Boolean condition on a load/increment/clear input. Example: the register AR receives a load pulse when

LOAD(AR) = T0 + T2 + D7'·I·T3

— i.e., during T0 (AR ← PC), T2 (AR ← address field) and T3 of an indirect memory-reference instruction. Collecting every such Boolean expression is the design of a hardwired control unit (Unit 3 takes this further).

3.6 The Interrupt Cycle

An enabled interrupt does not barge in mid-instruction. A flip-flop R is set when (IEN = 1) and a device raises its flag; the check happens only at instruction boundaries. When R = 1, the fetch is replaced by:

RT0: AR <- 0, TR <- PC        (save spot: return address to location 0)
RT1: M[AR] <- TR, PC <- 0
RT2: PC <- PC + 1, IEN <- 0, R <- 0, SC <- 0

Effect: return address stored at address 0, execution resumes at address 1 (the interrupt service routine's branch), and further interrupts are disabled until the ISR re-enables IEN. Why disable IEN? To prevent a second interrupt from overwriting the saved PC at location 0 — a classic "explain why" question.

🎯 Exam Focus

1. Draw/describe the flowchart of the complete instruction cycle including the indirect and interrupt cycles.
2. Write the RTL micro-operations for the fetch phase and explain why PC is incremented during T1.
3. Explain how timing signals T0–T3 are generated from a sequence counter and decoder. What does SC ← 0 achieve?
4. Give the full micro-operation sequence (T0…T5) for the instruction ADD with indirect addressing.
5. Derive the Boolean control function for the load input of AR in the basic computer.
6. Describe the interrupt cycle in RTL. Why is IEN cleared automatically during it?