1.1 Inside the CPU: The Register Set

The CPU is built from three cooperating parts: the register set (fast storage), the ALU (computation), and the control unit (sequencing). Registers exist because main memory is hundreds of times slower than the processor — every value the CPU is actively working on must live in a register.

Exam trap: MAR and MDR are not programmer-visible — they are internal interface registers. Questions like "which registers can an assembly programmer name?" exclude them.

1.2 General Register Organization

When a CPU has many registers, they are connected through a common bus system: two multiplexers (MUX A, MUX B) select the two source registers feeding the ALU, a decoder selects the destination register, and an operation code drives the ALU. One control word specifies an entire micro-operation:

Control word (14 bits, Mano's model):
| SELA (3) | SELB (3) | SELD (3) | OPR (5) |

Example: R1 <- R2 + R3
SELA = 010 (R2 onto bus A)
SELB = 011 (R3 onto bus B)
SELD = 001 (decoder enables load into R1)
OPR  = 00010 (ALU ADD)
Control word = 010 011 001 00010

Why it matters: the control word is exactly what the control unit (Unit 3) must generate every cycle — this is the bridge between datapath and control design.

1.3 Stack Organization

A stack CPU replaces named registers with a Last-In-First-Out stack (a register file or a memory region addressed by SP).

• PUSH X: SP ← SP + 1; M[SP] ← X (fills the stack upward; some machines decrement instead — read the question!).
• POP: value ← M[SP]; SP ← SP − 1.
• Arithmetic instructions take no address: ADD pops the top two items, adds, pushes the result.

Stack machines evaluate Reverse Polish Notation (RPN) naturally. For (3 + 4) × (5 − 2) → RPN: 3 4 + 5 2 − ×

PUSH 3        stack: 3
PUSH 4        stack: 3 4
ADD           stack: 7
PUSH 5        stack: 7 5
PUSH 2        stack: 7 5 2
SUB           stack: 7 3
MUL           stack: 21

1.4 Instruction Formats: 3, 2, 1 and 0 Addresses

An instruction = opcode + address fields. The number of explicit address fields is a fundamental design axis. Evaluate X = (A + B) × (C + D) in each style:

3-address:                 2-address:
ADD R1, A, B               MOV R1, A
ADD R2, C, D               ADD R1, B
MUL X, R1, R2              MOV R2, C
                           ADD R2, D
1-address (accumulator):   MUL R1, R2
LOAD A                     MOV X, R1
ADD  B
STORE T                    0-address (stack):
LOAD C                     PUSH A, PUSH B, ADD
ADD  D                     PUSH C, PUSH D, ADD
MUL  T                     MUL, POP X
STORE X

The trade-off (the "why"): fewer address fields → shorter instructions but longer programs and more memory references. Total program size = (instruction count) × (instruction length) — exams love asking which format gives the smallest program, and the answer depends on both factors, not just instruction count.

🎯 Exam Focus

1. List the programmer-visible and programmer-invisible registers of a CPU and state the function of each.
2. A CPU uses a 14-bit control word with SELA, SELB, SELD (3 bits each) and OPR (5 bits). Write the control word for R4 ← R1 − R2 (assume SUB = 00101).
3. Convert (A − B) × (C + D / E) into RPN and write the 0-address program to evaluate it.
4. Write programs to evaluate X = (A + B) × (C − D) using 3-, 2-, 1- and 0-address instruction formats.
5. Differentiate between general register organization and stack organization of a CPU (any five points).
6. Why do RISC processors favour the 3-address register format while older CISC machines used 1- and 2-address formats? Argue in terms of instruction width and memory traffic.