Computer Organization and Architecture — Previous Year Questions

PYQ papers for this course will be added here soon.

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• Important questions by unit

Frequently Asked Topics (by unit)

Unit 1 — Boolean Algebra, Logic Gates, K-Maps, Arithmetic Circuits

• State and prove De Morgan's theorems; explain the principle of duality
• Simplify a Boolean expression using Boolean laws (absorption, redundancy, consensus)
• Prove that NAND and NOR are universal gates; implement AND, OR, NOT, XOR using NAND only
• Numerical: simplify a 4-variable function using a K-map (SOP) and draw the logic diagram
• Numerical: obtain the minimum POS expression from a K-map
• Explain don't care conditions; solve a K-map with don't cares (BCD-based problems)
• Define prime implicant, essential prime implicant and redundant prime implicant
• Convert a standard SOP into canonical SOP / write Σm and ΠM forms from a truth table
• Design a half adder and a full adder; derive Sum and Carry with K-maps
• Design a full adder using two half adders and one OR gate
• Design a half/full subtractor; compare it with the adder
• Explain the 4-bit parallel binary adder/subtractor with the mode control M
• Explain the carry propagation delay and the carry look-ahead adder (generate and propagate)
• Numerical: 2's complement subtraction; overflow detection using C(n) XOR C(n−1)
• Number system conversions; binary/Gray code conversion; BCD and Excess-3

Unit 2 — Combinational Circuits and Flip-Flops

• Explain multiplexers; implement a Boolean function using an 8:1 and a 4:1 MUX
• Design an 8:1 MUX using 4:1 MUXes; design a 16:1 MUX using 4:1 MUXes
• Explain de-multiplexers; show that a decoder with enable is a DEMUX
• Design a 3-to-8 decoder; implement a full adder using a decoder and OR gates
• Design a 4-to-16 decoder using two 3-to-8 decoders
• Explain encoders and priority encoders; derive the equations of a 4-to-2 priority encoder
• Differentiate combinational and sequential circuits; latch and flip-flop
• Explain SR, D, JK and T flip-flops with truth tables, characteristic equations and excitation tables
• Explain the race around condition and how the master-slave flip-flop eliminates it
• Explain master-slave JK operation with a timing diagram; explain 1s catching
• Convert SR→JK, JK→D, JK→T, D→T, T→D, D→JK (any pair may be asked)
• Explain registers, shift registers (SISO, SIPO, PISO, PIPO) and the universal shift register
• Explain a register with parallel load using multiplexers
• Differentiate synchronous and asynchronous counters
• Design a MOD-5 / MOD-6 / MOD-10 synchronous counter using JK flip-flops
• Explain ring and Johnson counters; compare them with a binary counter

Unit 3 — Data Transfer Operations and Basic Computer Organization

• Explain Register Transfer Language; list its basic symbols with examples
• Explain arithmetic, logic and shift micro-operations with examples
• Explain the four applications of logic micro-operations (selective set, clear, complement, mask)
• Design a common bus system for four 4-bit registers using multiplexers (state the MUX size and count)
• Explain bus transfer using three-state buffers
• Explain memory read and write micro-operations (DR ← M[AR], M[AR] ← DR)
• Draw and explain an arithmetic circuit performing eight arithmetic micro-operations
• Draw and explain a 4-bit arithmetic logic shift unit with its function table
• Explain the instruction code format of the basic computer; direct vs indirect addressing
• List and explain the registers of the basic computer (AR, PC, DR, AC, IR, TR, INPR, OUTR)
• Explain the instruction cycle with all micro-operations for T0, T1, T2, T3
• Write the micro-operations for AND, ADD, LDA, STA, BUN, BSA and ISZ
• Explain the register-reference instructions of the basic computer
• Explain the interrupt cycle micro-operations
• Explain general register organization; encode given micro-operations into the control word (SELA, SELB, SELD, OPR)
• Explain register stack and memory stack with their PUSH and POP micro-operations
• Convert infix expressions to RPN and evaluate them on a stack
• **Evaluate X = (A+B)(C+D) using three-, two-, one- and zero-address instructions*
• Explain all addressing modes; solve the standard effective-address table numerical

Unit 4 — Input-Output Organization and Memory Organization

• Explain peripheral devices and the need for an I/O interface
• Differentiate isolated I/O and memory-mapped I/O
• Explain asynchronous data transfer: strobe control vs handshaking (with timing diagrams)
• Explain source-initiated and destination-initiated handshaking
• Explain asynchronous serial transfer; start/stop bit framing; baud rate numerical
• Explain the three modes of transfer: programmed I/O, interrupt-driven I/O and DMA
• Explain priority interrupt; daisy-chaining priority with the PI/PO/RF table
• Explain parallel priority interrupt with the interrupt register, mask register and priority encoder
• Explain DMA: registers, bus request/grant, burst vs cycle-stealing mode
• Explain the memory hierarchy; define locality of reference
• Differentiate SRAM and DRAM; explain the ROM family (PROM, EPROM, EEPROM, Flash)
• Numerical: how many chips are needed to build X memory from Y chips; draw the address map
• Explain magnetic disk organization (tracks, sectors, cylinders); disk capacity and access-time numericals
• Explain magnetic tape and optical storage; compare HDD and SSD
• Explain associative memory with the argument, key and match registers; solve a match example
• Explain cache mapping: direct, associative and set-associative; split a given address into fields
• Numerical: average memory access time from the hit ratio
• Explain replacement algorithms (FIFO, LRU, LFU, Optimal) and write policies (write-through, write-back)
• Explain virtual memory, paging and the page table; solve address-translation numericals
• Explain the TLB; effective memory access time numerical
• Explain page replacement algorithms with a reference string; explain Belady's anomaly and thrashing
• Differentiate paging and segmentation; explain segmented paging