2.1 Anatomy of a Bus
A bus is a shared set of lines connecting CPU, memory and I/O — cheap and extensible precisely because it is shared, which then creates the two problems this lesson solves: timing (when is data valid?) and arbitration (who may talk?).
| Sub-bus | Carries | Direction | Notes |
|---|---|---|---|
| Address bus | location being accessed | CPU → memory/I/O | width fixes addressable space: 32 lines → 2³² = 4 GB |
| Data bus | the data itself | bidirectional | width = word transferred per cycle (64 bits typical) |
| Control bus | READ/WRITE strobes, clock, interrupt, bus-request lines | mixed | orchestrates everything |
2.2 Synchronous vs Asynchronous Buses
Synchronous: all events are tied to a shared clock — the protocol is "address on edge 1, data valid on edge 3." Simple, fast logic, but every device must keep up with the clock, and the bus must be short (clock skew). Asynchronous: no shared clock; validity is negotiated by handshaking, so fast and slow devices coexist and the transfer takes exactly as long as the slave needs.
Two-way handshake (source-initiated write):
1. Master: places data, raises MSYN (master ready)
2. Slave : accepts data, raises SSYN (slave done)
3. Master: sees SSYN, drops MSYN (and data)
4. Slave : sees MSYN low, drops SSYN -> bus idle again| Aspect | Synchronous | Asynchronous |
|---|---|---|
| Timing reference | common clock | handshake signals |
| Speed matching | all locked to slowest device class | each transfer self-timed |
| Interface logic | simpler | more complex |
| Bus length | short (skew) | can be longer |
| Examples | classic memory buses, PCI | Unibus-style peripheral buses |
A simpler cousin: the strobe — one control pulse from source or destination announces the transfer, but with no acknowledgment the sender never learns whether data was actually taken; the handshake exists precisely to add that confirmation. This "strobe vs handshake" contrast is a standard 5-marker.
2.3 Bus Arbitration
With several potential bus masters (CPU, DMA controller, other processors), an arbiter must serialise access. Three centralized schemes:
- 1. Daisy chaining: one shared bus-request line; the grant signal snakes through devices in priority order, and the first requester absorbs it. Cheapest (few lines), fixed priority, starvation possible, one dead device severs the chain.
- 2. Polling: the arbiter broadcasts device numbers on poll lines (log₂ n lines); when a requesting device sees its own number it claims the bus. Priority = polling order, which software can rotate — flexible, but slower.
- 3. Independent requests: every device has its own request and grant pair into a priority encoder. Fastest arbitration, fully programmable priority, cost = 2n lines.
| Criterion | Daisy Chain | Polling | Independent |
|---|---|---|---|
| Extra lines | ~2 | log₂ n | 2n |
| Arbitration speed | slow (propagation) | slowest | fastest |
| Priority | fixed by position | rotatable | fully flexible |
| Fault sensitivity | high | moderate | low |
Distributed arbitration (no central arbiter — contenders drive their IDs on shared lines and the highest self-selects) appears in short-note form.
2.4 Standard Buses: PCI and USB
- PCI: classic parallel shared bus — 32/64 bits wide at 33/66 MHz (32-bit @ 33 MHz → 133 MB/s peak), multiplexed address/data lines, plug-and-play configuration space, centralized arbitration. Its scaling wall (skew across many parallel lines, shared bandwidth) led to PCI Express: serial point-to-point lanes (x1/x4/x8/x16), packet-switched, no sharing — e.g., a Gen3 lane ≈ 1 GB/s, so a x16 GPU slot ≈ 16 GB/s.
- USB (Universal Serial Bus): serial, host-centric tiered-star topology, up to 127 devices per host controller, hot-pluggable, supplies power. Generations: USB 1.1 → 12 Mbps, 2.0 → 480 Mbps, 3.0 → 5 Gbps, USB4 → 40 Gbps. Transfer types (control, interrupt, bulk, isochronous) map neatly onto device needs — isochronous (guaranteed bandwidth, no retry) for audio/video is the detail examiners fish for.
🎯 Exam Focus
- Name the three bus groups and state what a 20-bit address bus with a 16-bit data bus can address.
- Differentiate synchronous and asynchronous bus transfers; draw/describe the two-way handshake sequence.
- Why does a strobe-based transfer need upgrading to a handshake? What failure does it fix?
- Compare daisy chaining, polling and independent-request bus arbitration (lines, speed, priority, fault tolerance).
- Contrast PCI and PCI Express on topology, signalling and scalability.
- Describe USB's topology, device limit and the four transfer types with one use case each.