3.1 Two Philosophies of Instruction Set Design
CISC (Complex Instruction Set Computer) grew in the 1960s–70s when memory was tiny and expensive and compilers were weak: make single instructions do a lot (string copy, polynomial evaluate), close the "semantic gap" between high-level languages and hardware, and shrink program size.
RISC (Reduced Instruction Set Computer) was born from measurement (IBM 801, Berkeley RISC, Stanford MIPS, ~1980): dynamic traces showed compilers used a small simple subset of instructions ~80% of the time, while the complex ones mostly sat idle yet slowed the whole machine down (longer decode, microcode overhead). Conclusion: implement only simple instructions, make each blazingly fast, and let the compiler compose complexity.
3.2 The Comparison Table (Learn Every Row)
| Feature | RISC | CISC |
|---|---|---|
| Instruction count | few (dozens) | many (hundreds–thousands) |
| Instruction length | fixed (e.g., 4 bytes) | variable (x86: 1–15 bytes) |
| Instruction formats | very few, regular | many, irregular |
| Addressing modes | few (3–5) | many (12+) |
| Memory access | load/store only — ALU ops are register–register | ALU ops may reference memory directly |
| Registers | large file (32+) | fewer (x86 legacy: 8, x86-64: 16) |
| CPI | ~1 (pipeline-friendly) | multi-cycle, variable |
| Control unit | hardwired | microprogrammed (traditionally) |
| Code size | larger (more instructions) | smaller |
| Decoding | trivial, parallel | complex, sequential-ish |
| Compiler burden | heavy | lighter |
| Examples | ARM, MIPS, RISC-V, SPARC, PowerPC | x86/x86-64, VAX, Motorola 68000 |
The deep "why": fixed-length, regular instructions are what make deep pipelining and superscalar issue practical — the fetcher knows where every instruction begins, and the decoder is simple enough to replicate. CISC's variable lengths force serial-ish decode, the very bottleneck RISC removes.
3.3 Concrete Contrast: ARM vs x86
Add a memory variable into a register:
x86 (CISC): one instruction touches memory and adds
ADD EAX, [count]
ARM (RISC): load/store discipline, three registers
LDR R1, =count
LDR R2, [R1]
ADD R0, R0, R2- ARM: 16 (A32) / 31 (A64) general registers, fixed 4-byte instructions (plus compact Thumb), designed around low power per instruction — hence its dominance in phones and embedded devices.
- x86: decades of backward compatibility back to the 8086; instructions from 1 to 15 bytes; rich addressing (base + index × scale + displacement).
3.4 The Modern Convergence (Advanced Marks Live Here)
The war ended in a merger. Since the Pentium Pro (1995), x86 CPUs translate CISC instructions into RISC-like micro-operations (µops) in the decoder, then run them on a fast, pipelined, superscalar RISC-style core — "CISC outside, RISC inside." Meanwhile ARM added complex-ish features (NEON SIMD, hardware division). So today the ISA style matters less than the implementation; the real remaining CISC costs are decoder complexity and power, which is why ARM historically wins performance-per-watt while x86 retains the desktop/server software ecosystem.
Also mention-worthy: early RISC (SPARC) introduced register windows — overlapping register banks that make procedure call/return nearly free by renaming instead of saving/restoring — a distinguishing RISC feature examiners occasionally probe.
🎯 Exam Focus
- Differentiate RISC and CISC architectures (any eight points).
- What is the semantic gap? How did CISC try to close it, and why did RISC reject that approach?
- Why are fixed-length instructions and a load/store architecture essential for efficient pipelining?
- Compare ARM and x86 on registers, instruction length and target markets, with one code example.
- "Modern x86 processors are RISC machines in disguise." Justify with reference to micro-operations.
- Explain register windows and the problem they solve in RISC processors.