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Unit 1: Cache Memory

Lesson 12 of 34 in the free Fundamentals of IT & Computers notes on Siksha Sarovar, written by Rohit Jangra.

Unit I — Cache Memory

Cache memory is a small, ultra-fast memory located between the CPU and main memory (RAM). Its purpose is to store frequently accessed data and instructions so the CPU can retrieve them quickly without waiting for the slower main memory.

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Why Cache Memory?

The CPU operates far faster than RAM. Without cache, the CPU would spend most of its time waiting for data to arrive from RAM — a situation called a memory bottleneck.

ComponentTypical Speed
CPU (modern)3–5 GHz (sub-nanosecond per cycle)
Cache (L1)1–4 ns
RAM50–100 ns
HDD~5,000,000 ns (5 ms)

Cache bridges the speed gap between the CPU and RAM.

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Cache Levels

Modern CPUs have multiple levels of cache:

LevelLocationSizeSpeedShared?
L1 CacheInside each CPU core16–64 KBFastestNo (per core)
L2 CacheInside/near each core256 KB–1 MBFastNo (per core)
L3 CacheOn CPU die, shared4–64 MBModerateYes (all cores)

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How Cache Works — Hit and Miss

  1. CPU needs a data item.
  2. Cache Hit: Data is found in cache → returned in 1–4 ns. ✅
  3. Cache Miss: Data is not in cache → fetched from RAM → stored in cache for future use. ❌ (slower)

Hit Ratio = (Number of cache hits) / (Total memory accesses) A higher hit ratio means better performance.

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Cache Mapping Techniques

TechniqueDescription
Direct MappingEach RAM block maps to exactly one cache line
Fully AssociativeAny RAM block can go into any cache line
Set AssociativeCache divided into sets; block maps to a specific set but any line within it

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Cache Replacement Policies

When cache is full and a new block must be loaded, the CPU must decide which block to evict:

  • LRU (Least Recently Used) — Evict the block not used for the longest time.
  • FIFO (First In, First Out) — Evict the oldest block.
  • LFU (Least Frequently Used) — Evict the block accessed fewest times.
  • Random — Evict a random block.

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Write Policies

PolicyDescription
Write-ThroughData written to cache AND RAM simultaneously; always consistent
Write-BackData written to cache only; written to RAM only when evicted; faster but risk of inconsistency
Key Takeaway: Cache memory dramatically speeds up program execution by keeping frequently used data close to the CPU. The three levels (L1, L2, L3) offer a balance of speed and size. Cache hit ratio, replacement policy, and write policy are key exam concepts.